Passivation layer and its manufacturing method

Abstract

The invention discloses a passivation layer and a production method thereof. The passivation layer comprises an amorphous silicon layer (3), and a silicon dioxide layer (2) and a silicon oxynitride layer (1) which are formed on the amorphous silicon layer (3) in sequence, wherein the amorphous silicon layer (3) is formed on a semiconductor substrate and covers a metal wire (4) in the semiconductor substrate. The production method of the passivation layer comprises the following steps of: S01, depositing the amorphous silicon layer (3) on the semiconductor substrate, wherein the amorphous silicon layer (3) covers the semiconductor substrate and the metal wire (4) in the semiconductor substrate; S02, depositing the silicon dioxide layer (2) on the amorphous silicon layer (3); and S03, depositing the silicon oxynitride layer (1) on the silicon dioxide layer (2). The invention is applied to the technical field of semiconductor production and can enhance the yield rate of semiconductor chips.

Description

technical field [0001] The invention relates to the field of semiconductor chip manufacturing, in particular to a passivation layer formed on a semiconductor substrate and covering metal lines in the semiconductor substrate and a manufacturing method thereof. Background technique [0002] In the manufacturing process of semiconductor devices, the passivation of the device surface is one of the key technologies. Passivating the surface of the semiconductor device can reduce various charges in the oxide layer of the device, enhance the ability of the semiconductor chip to block ion contamination, protect the interconnection of the device inside the semiconductor chip and the electrical characteristics of the surface of the semiconductor chip, and prevent the semiconductor chip device from being damaged. mechanical and chemical damage. In the manufacturing process of semiconductor chip passivation layer, methods such as deposition and sputtering are often used. Due to the diff...

AI Technical Summary

Problems solved by technology

Due to the difference in Young's modulus and thermal expansion coefficient of the silicon dioxide layer 20 and the silicon oxynitride layer 10, the silicon dioxide layer 20 and the silicon oxynitride layer 10 of the above-mentioned process all apply shrinkage stress to the metal line 30, so that the passivation The adhesion between the layer and the metal wire 30 becomes poor, and even the metal wire 30 will be pulled out, and then there will be voids, cracks or shedding between the metal wire 30 and the passivation layer, which reduces the quality of the semiconductor chip. Rate

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