Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Cantilever type IC (Integrated Circuit) chip stack package of BT (Bismaleimide Triazine) substrate and production method of cantilever type IC chip stack package

A technology of chip stacking and BT substrates, which is applied in the field of electronic information automation components manufacturing, can solve the problems of increased line density and line length, difficult packaging, and increased short circuit of welding lines, so as to reduce the possibility, avoid short circuit of lines, and eliminate exposure The effect of the welding line

Active Publication Date: 2012-08-08
TIANSHUI HUATIAN TECH +1
View PDF3 Cites 24 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In addition, the increase in line density and line length in molded stack chip packages makes molded stack packages more difficult than traditional single chip packages
Rings of wire bonds of different layers, subject to varying traction forces, can create various changes in bond wire deflection, thereby increasing the possibility of bond wire shorting

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Cantilever type IC (Integrated Circuit) chip stack package of BT (Bismaleimide Triazine) substrate and production method of cantilever type IC chip stack package
  • Cantilever type IC (Integrated Circuit) chip stack package of BT (Bismaleimide Triazine) substrate and production method of cantilever type IC chip stack package
  • Cantilever type IC (Integrated Circuit) chip stack package of BT (Bismaleimide Triazine) substrate and production method of cantilever type IC chip stack package

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0114]The ultra-thin chip thinning machine of 8 inches and above with fine grinding and polishing functions is used for wafer thinning to obtain a wafer with a final thickness of 90 μm. During the thinning process, the rough grinding range of the wafer is from the original wafer Thickness + film thickness to 155μm + film thickness, coarse grinding speed is 50μm / min; fine grinding range is from 155μm + film thickness to 95μm + film thickness, fine grinding speed is 11μm / min; polishing range is from 95μm + film thickness Up to 90μm + film thickness, the polishing speed is 0.025μm / s.

[0115] Use A-WD-300TXB dicing machine to dice the thinned wafer to obtain IC chips; use anti-fragmentation software to control the feed speed ≤ 5mm / min during dicing; paste an IC on the substrate with insulating glue chip, and then use insulating glue to stack two layers of IC chips on the IC chip. The amount of insulating glue used between two adjacent IC chips ensures that the thickness of the gl...

Embodiment 2

[0141] The ultra-thin chip thinning machine of 8 inches and above with fine grinding and polishing functions is used for wafer thinning to obtain a wafer with a final thickness of 110 μm. During the thinning process, the rough grinding range of the wafer is from the original wafer Thickness + film thickness to 175μm + film thickness, coarse grinding speed is 85μm / min, fine grinding range is from 175μm + film thickness to 115μm + film thickness, fine grinding speed is 12μm / min; polishing range is from 115μm + film thickness To 110μm + film thickness, the polishing speed is 0.035μm / s.

[0142] Use the DAD3350 dicing machine to dice the thinned wafer to obtain IC chips; use anti-fragmentation software to control the feed speed of ≤6.5mm / min when dicing; paste an IC chip on the substrate with insulating glue, and then use The adhesive film is stacked and pasted on the IC chip with two layers of IC chips. The two layers of IC chips are all dislocated in the same direction, and the ...

Embodiment 3

[0144] Use an 8-inch and above ultra-thin chip thinning machine with fine grinding and polishing functions for wafer thinning to obtain a wafer with a final thickness of 100 μm: when thinning, the rough grinding range of the wafer is from the original wafer thickness +film thickness to 165μm+film thickness, coarse grinding speed is 120μm / min, fine grinding range is from 165μm+film thickness to 105μm +film thickness, fine grinding speed is 13μm / min; polishing range is from 105μm+film thickness to 100μm + film thickness, fine grinding speed is 0.025μm / s;

[0145]Use A-WD-300TXB dicing machine to dice the thinned wafer to obtain IC chips; use anti-fragmentation software to control the feed speed ≤ 8mm / min during the dicing process; paste an IC on the substrate with insulating glue chip, and then use insulating glue to stack and paste two layers of IC chips on the IC chip. The misalignment distance is 1.43mm; bake at a temperature of 175°C for 3 hours after loading the core. The ...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention discloses a cantilever type IC (Integrated Circuit) chip stack package of a BT (Bismaleimide Triazine) substrate and a production method of the cantilever type IC chip stack package. The package comprises a substrate carrier to which the BT substrate is adhered, wherein at least three layers of IC chips with the same appearance and size are stacked and adhered on the substrate; the back face of the substrate carrier is provided with a substrate back face bonding pad; the substrate back face bonding pad is connected with a substrate front face bonding pad; the surface of the substrate back face bonding pad is provided with bumps, solder and solder balls in sequence; two adjacent IC chips are arranged in a staggered way in the horizontal direction, the staggering distance is the same, and the IC chips are connected through a bonding wire; and a layer of IC chip on the substrate is connected with the substrate front face bonding pad through the bonding wire. The stack package is manufactured through the following steps of: thinning a wafer; scribing; loading the chip and roasting; performing plasma cleaning; performing pressure welding and plastic packaging; post-curing; mounting balls; performing reflux welding; and the like. According to the package, the height of each layer of bonding wire is reduced to the greatest extent, short circuiting between different annular layers of bonding wires is avoided, and the problems of stack package and unilateral bonding wire of the chips of the same size are solved.

Description

technical field [0001] The invention belongs to the technical field of electronic information automation component manufacturing, and relates to an IC chip stack package, in particular to a cantilever-type IC chip stack package with a BT substrate; the invention also relates to a production method of the stack package. Background technique [0002] With the ongoing trend towards miniaturization and increased performance, designers are constantly seeking the highest possible electrical functionality and performance in the smallest possible space. Two key limiting factors in this process are usually integration and I / O pin constraints. Chip space and connectivity constraints can be addressed at two different levels: the first is through die (or die)-level process scaling to achieve higher integration; the second is through stacking multiple A chip, that is, a stacked package or a stacked circuit board to achieve a higher level of integration. On the basis of existing chip ma...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
IPC IPC(8): H01L25/00H01L23/488H01L21/60
CPCH01L2924/15311H01L2224/32145H01L2224/48091H01L2224/73265H01L2224/45147H01L2924/181H01L2224/32225H01L2224/45144H01L2224/48145H01L2224/48227H01L2924/00014H01L2924/00012H01L2924/00
Inventor 朱文辉慕蔚郭小伟李习周
Owner TIANSHUI HUATIAN TECH
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com