Preparation method of double-layer silicon-on-insulator (SOI) mixed crystal orientation back-grid type transoid mode Si nanowire field effect transistor (NWFET)

Abstract

The invention provides a preparation method of a double-layer silicon-on-insulator (SOI) mixed crystal back-grid type transoid mode Si nanowire field effect transistor (NWFET). A power metal oxide semiconductor field effect transistor (PMOSFET) adopts a (110) surface crystal orientation silicon layer, and an N-type metal oxide semiconductor field effect transistor (NMOSFET) adopts a (100) surface crystal orientation silicon layer. In low temperature peeling technology, cracks are inclined to grow along the crystal orientation with increase of hydrogen pressure, therefore silicon layer peeling can be easily conducted along the (100) crystal orientation, and the layer transfer process is facilitated.

Description

technical field [0001] The invention relates to the technical field of semiconductor field effect transistors, in particular to a preparation process step of an SOI double-layer mixed crystal orientation gate-back type inversion mode SiNWFET. Background technique [0002] It has always been the goal pursued by the development of microelectronics industry to increase the working speed and integration of chips and reduce the power consumption density of chips by reducing the size of transistors. In the past forty years, the development of microelectronics industry has been following Moore's Law. At present, the physical gate length of field effect transistors is close to 20nm, and the gate dielectric is only a few layers thick of oxygen atoms. It is difficult to improve the performance by reducing the size of traditional field effect transistors, mainly because of the short channel Channel effect and gate leakage current deteriorate the switching performance of the transistor...

AI Technical Summary

Problems solved by technology

[0009] The present invention is aimed at the prior art, the existing semiconductor nanowire MOSFET can not realize the separation structure of NMOS and PMOS, can not adjust the gate work function and the gate resistivity for NMOS and PMOS respectively, and realize the separate structure for NMOS and PMOS The process of source-drain ion implantation is difficult and other defects Provide a preparation method for double-layer isolation mixed crystal orientation gate-back inversion mode SiNWFET on SOI

Images