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A three-strain all-planar soi BiCMOS integrated device and its preparation method

An integrated device, full-plane technology, used in semiconductor/solid-state device manufacturing, electric solid-state devices, semiconductor devices, etc., can solve the problems of complex preparation process, poor heat dissipation performance, low mechanical strength, etc.

Inactive Publication Date: 2015-12-02
XIDIAN UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Although GaAs and InP-based compound devices have superior frequency characteristics, their preparation process is more complicated than Si process, high cost, difficult to prepare large-diameter single crystal, low mechanical strength, poor heat dissipation performance, incompatibility with Si process and lack of SiO 2 Such passivation layer and other factors limit its wide application and development.

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  • A three-strain all-planar soi BiCMOS integrated device and its preparation method

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Experimental program
Comparison scheme
Effect test

Embodiment 1

[0108] Embodiment 1: Preparation of a 22nm three-strain, full-planar SOIBiCMOS integrated device and circuit with a conductive channel, the specific steps are as follows:

[0109] Step 1, epitaxial growth.

[0110] (1a) Select an SOI substrate, the lower support material of the substrate is Si, and the middle layer is SiO 2 , The thickness is 150nm, the upper layer material is doping concentration is 1×10 16 cm -3 N-type Si with a thickness of 100nm;

[0111] (1b) Using chemical vapor deposition (CVD) method, at 600℃, grow a layer of N-type epitaxial Si with a thickness of 50nm on the upper layer of Si material as a collector area, the doping concentration of this layer is 1× 10 16 cm -3 ;

[0112] (1c) Using chemical vapor deposition (CVD) method, at 600℃, grow a layer of SiGe with a thickness of 20nm on the substrate as the base region. The Ge composition of this layer is 15% and the doping concentration is 5×10 18 cm -3 ;

[0113] (1d) Using the method of chemical vapor deposition ...

Embodiment 2

[0167] Embodiment 2: Preparation of a 30nm three-strain, full-planar SOIBiCMOS integrated device and circuit with a conductive channel of 30nm, the specific steps are as follows:

[0168] Step 1, epitaxial growth.

[0169] (1a) Select an SOI substrate, the lower support material of the substrate is Si, and the middle layer is SiO 2 , The thickness is 300nm, the upper material is doping concentration is 5×10 16 cm -3 N-type Si with a thickness of 120nm;

[0170] (1b) Using the chemical vapor deposition (CVD) method, at 700℃, grow a layer of N-type epitaxial Si with a thickness of 80nm on the upper Si material as a collector area, the doping concentration of this layer is 5× 10 16 cm -3 ;

[0171] (1c) Using the chemical vapor deposition (CVD) method, at 700℃, a SiGe layer with a thickness of 40nm is grown on the substrate as the base region. The Ge composition of this layer is 20% and the doping concentration is 1×10 19 cm -3 ;

[0172] (1d) Using chemical vapor deposition (CVD) method...

Embodiment 3

[0226] Embodiment 3: Preparation of a three-strain, full-planar SOIBiCMOS integrated device and circuit with a 45nm conductive channel. The specific steps are as follows:

[0227] Step 1, epitaxial growth.

[0228] (1a) Select an SOI substrate, the lower support material of the substrate is Si, and the middle layer is SiO 2 , The thickness is 400nm, the upper material is doping concentration is 1×10 17 cm -3 N-type Si with a thickness of 150nm;

[0229] (1b) Using chemical vapor deposition (CVD) method, at 750℃, grow a layer of N-type epitaxial Si layer with a thickness of 100nm on the upper Si material as the collector area, the doping concentration of this layer is 1× 10 17 cm -3 ;

[0230] (1c) Using the chemical vapor deposition (CVD) method, at 750℃, a SiGe layer with a thickness of 60nm is grown on the substrate as the base region. The Ge composition of this layer is 25% and the doping concentration is 5×10 19 cm -3 ;

[0231] (1d) Using chemical vapor deposition (CVD) method, a...

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Abstract

The invention discloses a three-strained fully planar SOI BiCMOS integrated device and a preparation method. The preparation method comprises continuously growing an N-Si layer, a P-SiGe layer and an N-Si layer on an SOI substrate, preparing deep trench isolation, etching a collector region, a base region and a shallow trench isolation region by lithography respectively, carrying out ion implantation, forming a collector, base and emitter contact region, and finally forming a SiGe HBT (heterojunction bipolar transistor) device; etching a trench in the active region of an NMOS (n-type metal oxide semiconductor) by lithography, growing four material layers in the trench, and preparing a gate dielectric layer and gate polysilicon on the active region of the NMOS device to obtain the NMOS device; etching a trench in the active region of a PMOS (p-type metal oxide semiconductor) by lithography, growing three material layers in the trench, and preparing a drain and a gate on the active region of the PMOS device to obtain the PMOS device; and etching leads by lithography to obtain the three-strained fully planar SOI BiCMOS integrated device and circuit. The preparation method provided by the invention adopts the self-alignment process, and fully utilizes the characteristics that the electron mobility of a tensile strained Si material is higher than that of a bulk Si material and that the hole mobility of a compressive strained SiGe material is higher than that of the bulk Si material so as to prepare the performance-enhanced three-strained fully planar SOI BiCMOS integrated circuit.

Description

Technical field [0001] The invention belongs to the technical field of semiconductor integrated circuits, and in particular relates to a three-strain full-planar SOIBiCMOS integrated device and a preparation method. Background technique [0002] Integrated circuits are the cornerstone and core of the economic development of the information society. As the U.S. engineering technology community recently mentioned the fifth electronic technology among the 20 greatest engineering achievements in the world in the 20th century, “from vacuum tubes to semiconductors and integrated circuits, it has become the cornerstone of intelligent work in various industries today.” One of the typical products that best reflects the characteristics of the knowledge economy. At present, the electronic information industry based on integrated circuits has become the world's largest industry. With the development of integrated circuit technology, the clear boundaries between complete machines and compo...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/12H01L21/84
Inventor 王斌宣荣喜胡辉勇张鹤鸣吕懿周春宇宋建军郝跃
Owner XIDIAN UNIV