Gallium nitride (GaN) base enhancement device containing ferroelectric layer and preparation method thereof
An enhanced ferroelectric layer technology, applied in the field of microelectronics, can solve the problems of device performance degradation, output current and transconductance reduction, preparation process incompatibility, etc., and achieve the effect of performance improvement
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Embodiment 1
[0034] GaN-based enhancement-mode devices with ferroelectric layers, including AlGaN / GaN / Al 2 o 3 A semiconductor heterostructure substrate on which a ZnO buffer layer and epitaxial LiNbO 3 type ferroelectric thin film layer, ZnO buffer layer is set on the substrate and epitaxial LiNbO 3 Type ferroelectric thin film layer; AlGaN with Al x Ga 1-x N means, x is the molar content of Al, x=1. GaN or AlGaN is oriented along the (0001) direction.
[0035] The material of the ZnO buffer layer is ZnO doped with Al element.
[0036] Epitaxial LiNbO 3 The material of the ferroelectric thin film layer is Mg-doped LiNbO 3 .
Embodiment 2
[0038] GaN-based enhancement-mode devices with ferroelectric layers, including AlGaN / GaN / Al 2 o 3 A semiconductor heterostructure substrate on which a ZnO buffer layer and epitaxial LiNbO 3 type ferroelectric thin film layer, ZnO buffer layer is set on the substrate and epitaxial LiNbO 3 Type ferroelectric thin film layer; AlGaN with Al x Ga 1-xN means, x is the molar content of Al, x=0.5. GaN or AlGaN is oriented along the (0001) direction.
[0039] The material of the ZnO buffer layer is ZnO.
[0040] Epitaxial LiNbO 3 The material of the ferroelectric thin film layer is LiNbO 3 .
Embodiment approach
[0041] see Figure 5 , the embodiment of the preparation process of the present invention is as follows:
[0042] (1) Using BCl 3 / Cl 2 Plasma etching technology performs mesa etching on AlGaN / GaN thin film substrates. Then, ohmic electrodes were prepared in the source and drain regions by electron beam evaporation process;
[0043] (2) Covering the gate region with photoresist through photolithography technology. At this time, the grid length is d 1 . Then, deposit the first mask layer on the surface of the substrate; the material of the mask layer is Si 3 N 4 or SiO 2 , deposited at room temperature, its thickness depends on the thickness of the ferroelectric layer, generally controlled between 200~300nm.
[0044] (3) Removing the cover layer of the gate region, including the photoresist and the first layer of mask layer material covered thereon;
[0045] (4) Through photolithography again, the gate region formed in the previous step is covered with photoresist. A...
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