Manufacture method of MOM capacitor

Abstract

The invention discloses a manufacture method of an MOM (Mass Optical Memory) capacitor, which is used for increasing the capacitance density of an MOM capacitor structure. The MOM capacitor structure comprises a capacitor area and a copper interconnecting area; the MOM capacitor structure forms a corrosion barrier layer, a low dielectric constant dielectric layer and a metal hard mask layer after thin film deposition, wherein the metal hard mask layer comprises a buffer layer, a mask layer and an overlying layer. The manufacture method particularly comprises the steps of: 1, growing an etching regulating layer made of same materials with a buffer layer on the buffer layer; 2, defining a photomask in which the MOM capacitor is; 3, removing the etching regulating layer of an area in which the MOM capacitor is; and 4, carrying out through hole formation, metal copper filling and chemical mechanical grinding of the MOM capacitor structure by using a general process. The invention has the advantages that through introducing the etching regulating layer, the thickness of the residual dielectric layer of an MOM capacitor area is reduced, therefore, the purpose of increasing capacitance density is achieved; and through regulating the thickness and the etching parameter of the etching regulating layer, a proper capacitance density is achieved.

Description

technical field [0001] The invention relates to the technical field of MOM capacitors, in particular to a manufacturing method of MOM capacitors. Background technique [0002] With the continuous improvement of semiconductor integrated circuit manufacturing technology, the continuous improvement of performance is also accompanied by the process of device miniaturization and miniaturization. Capacitors are important components of integrated circuits, widely used in chips such as memory, microwave, radio frequency, smart cards, high voltage and filtering. [0003] There are various capacitor structures in integrated circuit chips, such as MOS (metal-oxide-semiconductor Field, metal-oxide-semiconductor) field effect tube capacitors, PIP (poly-insulator-poly, polyethylene-insulator-polyethylene) capacitors , variable junction capacitance and MIM (metal-insulat0r-metal, metal-insulator-metal) capacitance and MOM (metal-oxide-metal, metal-oxide-metal) capacitance in the back-end ...

AI Technical Summary

Problems solved by technology

However, because the dielectric layer is too thick, the capacitance density is very low, and it is difficult to reach the level of ordinary single-layer capacitors even if multiple layers are stacked.

In addition, this method needs to occupy the space of multiple interconnection layers, and no other interconnection lines can exist in all the interconnection layer areas where these capacitors exist, so the available wiring area in the back section of the chip is greatly reduced, which is not conducive to the miniaturization of the device. It also brings difficulties to the circuit design

Images