NMOS (N-channel metal oxide semiconductor) device, with GaAs material growing in silicon grooves, based on ART (aspect radio trapping ) structure

Abstract

The invention discloses a preparation method of an NMOS (N-channel metal oxide semiconductor) device and the corresponding NMOS device. The preparation method includes the steps of S1, selecting a silicon substrate which deviates 6-10 degrees in a direction from (100) to (111), and growing a SiO2 layer on the silicon substrate; S2, etching the SiO2 layer to form a plurality of grooves with aspect ratio larger than 2 on the SiO2 layer, and allowing the bottom of each groove to be exposed out of the silicon substrate; S3, under a growth pressure of 100-150 mBar, using a MOCVD (metal organic chemical vapor deposition) process to sequentially grow a barrier layer, a buffer layer and a top layer in each groove; and S4, producing a source, a drain and a grid on each top layer. Mismatch dislocation at an interface and antiphase domain boundary are stopped at a SiO2 wall, hetero-junction interface defect extension is restrained effectively, epitaxial layer quality is improved, and good device quality is achieved when an epitaxial layer is used at the substrate of the NMOS.

Description

technical field [0001] The invention relates to a method for preparing a silicon-based NMOS device and a corresponding NMOS device. Specifically, the present invention relates to the combination of MOCVD and high aspect ratio trench confinement technology (Aspect RatioTrapping, ART) to grow material structures and prepare silicon-based NMOS devices. Background technique [0002] In the past ten years, large-scale integrated circuit technology has advanced by leaps and bounds, which is largely related to the use and development of MOS transistors. Since the MOS transistor entered the integrated circuit manufacturing industry, through continuous development, it has become one of the most important electronic devices in the industry. However, the development of the electronic information industry has put forward higher requirements for integrated components. According to the prediction of the International Semiconductor Industry Technology Development Blueprint (ITRS2009), the...

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Problems solved by technology

However, with the development of integrated circuit technology below the 22nm technology node, silicon (Si) integrated circuit technology is limited by a series of basic physical problems and process technology in terms of speed, power consumption, integration, reliability, etc., and Expensive production line construction and manufacturing costs make the integrated circuit industry face huge investment risks. The traditional silicon CMOS technology adopts "downsizing" to achieve smaller, faster, and cheaper logic and storage devices. The development model has been difficult to maintain

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