Unlock instant, AI-driven research and patent intelligence for your innovation.

Size encapsulation structure and encapsulation technology of light-emitting diode (LED) wafer level chip

A technology of chip size packaging and packaging technology, which is applied in the direction of electrical components, circuits, semiconductor devices, etc., can solve the problems of poor product consistency, low packaging efficiency, and many thermal interfaces, so as to improve consistency, improve production efficiency, and improve heat dissipation effect of ability

Active Publication Date: 2013-07-03
刘胜
View PDF7 Cites 14 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The traditional packaging technology uses lead frames to package individual chips, which has low packaging efficiency, poor product consistency, and many thermal interfaces that lead to poor heat dissipation

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Size encapsulation structure and encapsulation technology of light-emitting diode (LED) wafer level chip
  • Size encapsulation structure and encapsulation technology of light-emitting diode (LED) wafer level chip
  • Size encapsulation structure and encapsulation technology of light-emitting diode (LED) wafer level chip

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0045] Embodiments of the present invention are further described below in conjunction with the accompanying drawings:

[0046] Fabrication of LED wafer bonding layer structure: photolithography and development on the LED epitaxial layer, transfer the designed electrode pattern to the LED epitaxial layer, etch GaN by dry etching process, the etching depth is n-type GaN7 and multi-layer The sum of the thicknesses of the quantum well 8, expose n-type GaN6, make an insulating layer between n-type GaN6 and p-type GaN7, metallize n-type GaN6 and p-type GaN7, and pad 4 includes Ni, Ag, Au, ITO and other metals . Photolithography, development, and fabrication of the bonding layer 5, the fabrication methods may include processes such as deposition, printing, and electroplating. The material of the bonding layer 5 may include: Sn-Ag, Sn, Ag, Au, Sn-Ag-Cu, Pb-Sn, Au-Sn and other metals. Such as Figure 8 shown. The shape of the bonding layer 5 can be two pieces of positive and negat...

Embodiment 2

[0052] Embodiment 2 is the same as Embodiment 1, except that the fluorescent layer on the sapphire is formed by a printing process, and its process steps are before all processes.

Embodiment 3

[0054] The third embodiment is the same as the first embodiment, except that the bonding process between the LED wafer and the silicon substrate is realized by a reflow process.

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

PropertyMeasurementUnit
Thicknessaaaaaaaaaa
Login to View More

Abstract

The invention discloses a size encapsulation structure and encapsulation technology of a light-emitting diode (LED) wafer level chip. The size encapsulation structure comprises a silicon substrate, an LED wafer, bonding layers, an LED outward extension layer, an insulating layer, a reflecting layer, a welding disc, a fluorescent powder layer and a lens and is characterized in that a through hole is arranged in the silicon substrate and the insulative layer is deposited on the back of the silicon substrate. Metal is filled in the through hole to achieve vertical electrical connection. The welding disc and the reflecting layer are arranged on the front of the silicon substrate. An electrode is arranged on the back of the silicon substrate. An n electrode and a p electrode are arranged on the LED outward extension layer. Bonding layers are arranged on the n electrode and the p electrode. The LED wafer is bonded with the silicon substrate with the through hole. The fluorescent powder layer is coated on the LED wafer. A lens array or a silicon protection layer is arranged on the LED wafer. The size encapsulation structure and the encapsulation technology of the LED wafer level chip has the advantages that the size of the LED is reduced after encapsulation, heat and electricity separation is achieved by means of the conducting vertical connection structure and the technology, the radiating performance of the LED component is improved, by means of rotational coating technology and printing technology, shape-keeping coating of the LED is achieved and uniformity in encapsulating LEDs is improved.

Description

technical field [0001] The invention relates to a semiconductor device and a manufacturing process, in particular to an LED wafer-level chip size packaging structure and a process method. Background technique [0002] Compared with traditional light sources, LEDs, as the fourth-generation light sources, have the advantages of high efficiency, energy saving, high brightness, longevity, and environmental protection, and are playing an increasingly important role in the fields of lighting and display. At present, LED packaging technology presents a diversified development trend. The traditional packaging technology uses lead frames to package individual chips. The packaging efficiency is low, the product consistency is poor, and there are many thermal interfaces, resulting in poor heat dissipation. With the help of Through Silicon Via (TSV) technology in the IC process, LED chips are packaged in a system-level package, which facilitates the integration of LED devices and circu...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
IPC IPC(8): H01L33/48H01L33/54H01L33/62H01L33/64
Inventor 刘胜陈照辉周圣军王恺
Owner 刘胜