Dynamic random access memory and manufacturing method, semiconductor package and packaging method

Abstract

The invention discloses a dynamic random access memory, a manufacturing method, a semiconductor package and a packaging method. The DRAM manufacturing method includes: providing a memory wafer, having a memory die on the memory wafer, a top metal layer on the memory die, power pads, signal pads and micro pads on the top metal layer, leading out the memory The internal bus of the bare chip is electrically connected to the micro-pad; the memory wafer is repaired; if the yield rate of the memory wafer is greater than or equal to the predetermined threshold, the micro-pad is rearranged to form a butt pad, and the butt pad and the micro-pad The pad and the power pad are electrically connected. A semiconductor packaging method, comprising: a first wafer provided with a dynamic random access memory; a second wafer provided with a logic chip; the first wafer and the second wafer are electrically connected through a suitable butt pad to realize the wafer round level package. The invention does not make major changes to the DRAM structure, but improves the data bandwidth of the DRAM and ensures a high yield rate at the same time.

Description

technical field [0001] The invention relates to the field of semiconductors, in particular to a dynamic random access memory and a manufacturing method thereof, a semiconductor package and a packaging method thereof. Background technique [0002] Dynamic Random Access Memory (DRAM, Dynamic Random Access Memory) has the characteristics of large capacity, high speed, low unit cost, etc., so it is extremely versatile. After long-term development, DRAM has developed a variety of products, such as: in high-performance applications, it has evolved from the first generation of DDR to the fifth generation of DDR5, and in low-power applications, it has evolved from LPDDR to LPDDR2. [0003] like figure 1 As shown, the current mainstream DRAM generally includes a storage array 10 , a control logic circuit 20 and an interface conversion logic circuit 30 . The memory array 10 includes a large number of memory cells for storing data, occupying the largest area among DRAMs. The storage...

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Problems solved by technology

But if the yield rate of DRAM is only 60%, the final yield rate is only 58.8%, wasting too many qualified SoC chips, and the gain outweighs the gain

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