Method for preparing TiN through utilizing physical vapor deposition (PVD)

A technology of titanium nitride and wafers, applied in the field of PVD preparation of TiN thin films
CN103540893AInactive Publication Date: 2014-01-29INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
INST OF MICROELECTRONICS CHINESE ACAD OF SCI
Publication Date
2014-01-29
Estimated Expiration
Not applicable · inactive patent

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Abstract

Disclosed is a method for preparing TiN through PVD,comprising: in a vacuum environment inflated with nitrogen and a noble gas, making the noble gas to have glow discharge to form noble gas ions; nitridizing a chip surface and a Ti target surface by using the nitrogen; the noble gas ions bombarding the Ti target surface under electric field acceleration for sputtering TiN and Ti ions; the TiN depositing, under the action of the electric field, on the chip surface to form a TiN layer, and the Ti ions being incident on the chip surface to make the TiN layer to have a stress. The method is characterized in that: kinetic energy when the Ti ions are incident on the chip surface is increased to improve a non-crystallization rate of the TiN layer, thereby increasing the stress of the TiN layer. The method for preparing TiN through PVD according to the present invention improves kinetic energy when the Ti ions are incident on the chip surface by controlling process parameters to improve the non-crystallization rate of the TiN, thereby increasing the stress of the TiN thin film.
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Description

technical field

[0001] The invention relates to a method for manufacturing a semiconductor device, in particular to a method for preparing a TiN thin film by PVD. Background technique

[0002] With the continuous development of large-scale integrated circuit technology and the continuous improvement of circuit integration, the feature size of MOSFET devices has reached the technical node below 22nm. In fact, after entering the 90nm technology node, it has become more and more difficult to simply reduce the gate length to meet the requirements of Moore's Law. Because with the shortening of the gate length, the channel doping scattering, strong field effect and parasitic resistance introduced by the channel heavy doping used to suppress the short channel effect increase, resulting in a decrease in the channel carrier mobility, which affects the The improvement of the electrical performance of the device. In this context, strain engineering emerged as the times require, and i...

Claims

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