An ultra-low loss device of drain-source region dielectric/pn junction isolation front gate p/n-mosfet radio frequency switch based on soi process

Abstract

The invention discloses a drain-source area medium / PN junction isolated front-gate P / N-MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) radio frequency switch ultralow-loss device based on an SOI (Silicon On Insulator) technology, wherein SOIP(N)-MOSFET device source and drain regions are modified, PN junctions or dielectric capacitors are produced in the source and drain regions, the junctions in source regions are large in depth, N(P) type doping or mediums are implanted in the source regions to form PN junctions or dielectric capacitors so as to form isolation to the voltage of direct current applied by a drain; through the biasing arrangement of the MOS and back-gate, the back-gate MOSFET channel is in a conducting state, altering current signals at the front-gate P(N)-MOSFET drain region are coupled to back-gate MOSFET; since the back-gate works in the conducting state, adjustment to impedance in ON state of the front-gate MOSFET is formed due to the structure, so that the radio frequency loss of the front-gate MOSFET serving as the switch applying to the ON state is reduced; when the back-gate MOSFET device generates negative impedance due to that the device generates self-heating effect, and the back-gate MOSFET works in the amplification state, front-gate coupling signals is directly amplified, energy loss in the ON state of the front-gate is compensated, and thus the ultrlow / zero-loss radio frequency switch is formed.

Description

technical field [0001] The invention belongs to the field of semiconductor technology, and relates to a radio frequency switch based on SOI (semiconductor-on-insulator technology drain-source region dielectric / diode isolation front gate P(N)-MOSFET (P(N) type metal-oxide-semiconductor transistor) ultra-low loss device. Background technique [0002] Due to the use of dielectric isolation, SOI P(N)-MOS devices eliminate the latch-up effect, and its unique insulating buried layer structure greatly reduces the parasitic effects of the device, greatly improving the performance of the circuit, with parasitic capacitance The advantages of small size, high integration density, fast speed, simple process, and small short channel effect are widely used in low voltage, low power consumption, high speed, radiation resistance, high temperature resistance and other fields. The structure of a conventional SOI P(N)-MOSFET device is a sandwich structure of an insulating substrate, a buried ...

AI Technical Summary

Problems solved by technology

When the SOI P(N)-MOSFET device works normally, the channel formed by the conduction of source and drain is only on the top surface of the N(P)-type channel region, and it is a lateral channel, and the gate field plate covers the gate oxide layer, resulting in high on-state power consumption, low device efficiency, and high loss when used as a radio frequency switch, which is not conducive to improving the overall performance of the device and system

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