Planar DMOS device, preparation method thereof, and electronic device
A planar, device technology, used in semiconductor/solid-state device manufacturing, semiconductor devices, circuits, etc., can solve the problems of large leakage current and difficult control in practical operation, and achieve a reduction in leakage current, stable withstand voltage, and reduced concentration. Effect
Active Publication Date: 2014-06-04
FOUNDER MICROELECTRONICS INT
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Problems solved by technology
Due to the introduction of some mobile ions and some interface charges during the manufacturing process, the BV (withstand voltage) drifts during the normal temperature test on the wafer (silicon wafer), and the leakage current is too large during the high temperature test. See figure 2 (Ids-drain-source current, Vds-drain-source voltage)
The current conventional approach is to improve the process conditions of the device, reduce contamination in the process engineering, reduce the number of positive charges in the oxide layer and the concentration of interface traps to eliminate this effect, but it is difficult to control in practice
Method used
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Embodiment 1
[0041] In this embodiment, the steps for preparing a planar DMOS device are as follows:
[0042] Step 1: Clean the wafer, and grow a layer of silicon dioxide with a thickness of about 8000 angstroms on the wafer.
[0043] Step 2: Apply a layer of photoresist, develop and etch the place where boron ions need to be implanted, implant boron with a dose of 1e14, a voltage of 60KeV, and an angle of 7. The same dose of boron ions is completed simultaneously with the implantation of boron ions in the chip area.
[0044] Step 3: Apply a layer of photoresist, develop and etch in the active area of DMOS, implant phosphorus (p) in the active area, the dose is 3e12, the voltage is 140Kev, and the angle is 7. For the Si substrate and start growing the SiO2.
[0045] Step 4: Grow a layer of silicon dioxide with a thickness of 1200 angstroms and a layer of polysilicon with a thickness of 7000 angstroms on the entire wafer, and then etch, leaving silicon dioxide and polysilicon only where...
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Abstract
The invention relates to a planar DMOS device, a preparation method thereof, and an electronic device; and a chip part or all surrounding parts are connected with an extended boron ion implanted region. The invention also relates to the preparation method of the planar DMOS device. While a process condition and chip area are not changed in the invention, an outer ring is designed in a scribing groove so as to enclose or partially enclose the entire chip; movable charges generated in the processing process are eliminated and the concentration of an interface trap is reduced; and when the planar DMOS device is tested on a wafer (silicon wafer) in a normal temperature, the BV (voltage resistance) is stable, and the leakage current is greatly reduced when the high temperature test is carried out.
Description
technical field [0001] The invention relates to a planar DMOS device, its preparation method and electronic equipment. Background technique [0002] One of the key parameters of planar DMOS (Double Diffused Metal Oxide Semiconductor Transistor) devices is BV (withstand voltage), and the part that bears high voltage is its voltage divider ring, which is generally composed of P+body-P type implantation area, poly-multi crystalline and metal- metal composition (such as figure 1 ). The function of the voltage divider ring is to increase the radius of curvature of the junction and minimize the surface electric field. Due to the introduction of some mobile ions and some interface charges during the manufacturing process, the BV (withstand voltage) drifts during the normal temperature test on the wafer (silicon wafer), and the leakage current is too large during the high temperature test. See figure 2 (Ids-drain-source current, Vds-drain-source voltage). The current convention...
Claims
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Patent Timeline
Login to View More IPC IPC(8): H01L29/78H01L29/06H01L21/336H01L21/265
CPCH01L21/266H01L29/0657H01L29/0684H01L29/66681H01L29/7801
Inventor 文燕陈建国潘光燃何昌
Owner FOUNDER MICROELECTRONICS INT