Copper bump package interconnection structure and method filled with double-layer underfill glue

Abstract

The invention relates to a packaging and interconnecting structure and method for copper protruded points filled up with double layers of underfill. The packing and interconnecting structure is characterized in that the chip end is filled up with the first layer of underfill, the first layer of underfill is manufactured on a wafer through spin coating process, the substrate end is filled up with the second layer of underfill, the substrate end is filled through capillary effects after flip-chip welding is finished, the glass transition temperature and the Young modulus of the first layer of underfill are lower than those of the second layer of the underfill, a chip and a substrate are connected through the copper protruded points and tin-contained solder protruded points to achieve high-density connection, and the copper protruded points are manufactured in twice to guarantee that the first layer underfill is completely filled and the contact between the protruded points and the tin-contained solder is enough. The whole technological process is compatible with existing IC process and has higher vertical interconnection density, better electric connection characteristics and higher mechanical stability. Heating thermal circulation tests show that the service life of chips of the packaging structures is greatly prolonged.

Description

technical field [0001] The invention relates to a double-bottom glue-filled copper bump package interconnection structure and method, belonging to the field of advanced electronic packages. Background technique [0002] In flip-chip soldering, bumps are needed to connect the chip and the substrate. Due to the large difference in thermal expansion coefficient between materials, a large thermal stress will be generated. In order to ensure the integrity of the bumps, it is necessary to fill the underfill to make the concentrated stress get out. dispersion. For traditional tin-containing solders and organic substrates, the underfill is required to have a higher glass transition temperature, a larger Young's modulus and thermal expansion coefficient. [0003] With the development of IC technology in the direction of smaller size and higher density, people pay more and more attention to the delay effect between interconnection lines, which has become a bottleneck that limits the ...

AI Technical Summary

Problems solved by technology

At present, the industry still uses the traditional method for underfill filling, which cannot effectively reduce the stress on the chip end, resulting in unsatisfactory reliability of copper bumps.

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