An electrostatic discharge protection structure

Abstract

The invention discloses an electrostatic discharge protection structure, which comprises a well region within a substrate, wherein the well region has doping ions of a first conductivity type therein and is electrically connected with a ground terminal; a second doped region within the substrate, wherein the second doped region is located on the surface of the well region, and has doping ions of a second conductivity type therein, wherein a doping concentration in the second doped region is higher than that in the well region; a first doped region within the substrate, wherein the first doped region is located on the surface of the second doped region, and a surface of the first doped region is flush with the substrate surface, wherein the first doped region has doping ions of a first conductivity type therein and is electrically connected with an electrostatic discharge input terminal, and wherein a doping concentration in the first doped region is higher than that in the second doped region, and the doping concentration difference between the first doped region and the second doped region is smaller than that between the second doped region and the well region. The electrostatic discharge protection structure has a low breakdown voltage so as to be improved in a protective capability.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to an electrostatic discharge protection structure. Background technique [0002] As semiconductor chips are used more and more widely, there are more and more factors that cause semiconductor chips to be damaged by static electricity. In existing chip designs, electrostatic discharge (ESD, Electrostatic Discharge) protection circuits are often used to reduce chip damage. The design and application of existing ESD protection circuits include: Gate Grounded NMOS (GGNMOS) protection circuits, Silicon Controlled Rectifier (SCR) protection circuits, lateral diffusion field effect transistors ( Laterally Diffused MOS, LDMOS) protection circuit, etc. [0003] figure 1 It is a schematic cross-sectional structure diagram of an existing gate-grounded N-type field effect transistor protection structure, including: a substrate 10; a P-type well region 11 located in the s...

AI Technical Summary

Problems solved by technology

[0005] However, with the development of semiconductor technology, the size of semiconductor devices continues to shrink, so that the energy consumption of the chip is continuously reduced, and its operating voltage is continuously reduced. However, the breakdown voltage of the existing gate-grounded N-type field effect transistor is too high, and Unable to protect chips or semiconductor devices with low operating voltage from electrostatic damage

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