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ldmos device and manufacturing method

A device and manufacturing process technology, applied in the field of LDMOS device manufacturing, can solve problems such as low on-resistance, reduce device breakdown voltage, etc., achieve large on-resistance, increase breakdown voltage, and reduce on-resistance

Active Publication Date: 2017-08-08
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

It is usually necessary to add an additional N-type implant in the drift region of the device to make the device have a lower on-resistance, and this method will reduce the breakdown voltage of the device

Method used

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Embodiment Construction

[0048] figure 1 It is a schematic structural diagram of an LDMOS device in an embodiment of the present invention; the LDMOS device in an embodiment of the present invention is an N-type LDMOS device, including:

[0049] The N+ buried layer 102 is formed on the P-type silicon substrate 101 .

[0050] The P+ buried layer 103 is formed on a part of the N+ buried layer 102 , and the bottom of the P+ buried layer 103 is in contact with the N+ buried layer 102 .

[0051] The N-type epitaxial layer 104 is formed on the surface of the silicon substrate 101 , and the bottom of the N-type epitaxial layer 104 is respectively in contact with the N+ buried layer 102 and the P+ buried layer 103 .

[0052] The P-type diffusion layer 105 is formed in the N-type epitaxial layer 104 on the top of the P+ buried layer 103, and the P-type impurities of the P-type diffused layer 105 are transferred from the P+ buried layer 103 to the N-type epitaxial layer. Diffusion formation in 104.

[0053] ...

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Abstract

The invention discloses an LDMOS device. In the drift region composed of N-type epitaxial layers, an N-type injection layer formed by high-dose N-type impurity implantation is added, and the N-type injection layer is formed under the side close to the source end of the N-type injection layer. There is a P-type auxiliary depletion layer formed by high-dose P-type impurity implantation, and a P-type diffusion layer formed by diffusion of impurities in the P+ buried layer in the N-type epitaxial layer is formed on the side of the N-type implantation layer close to the source end. The invention also discloses a manufacturing method of the LDMOS device. The invention can reduce the conduction resistance of the device, increase the conduction current of the device, reduce the surface electric field strength of the drift region, increase the breakdown voltage of the device, and can be integrated in the BCD process without adding additional process cost.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a lateral double-diffused metal oxide semiconductor field effect transistor (lateral double-dif fused MOSFET, LDMOS) device, and the invention also relates to a manufacturing method of the LDMOS device. Background technique [0002] Double diffused metal oxide semiconductor field effect transistor (DMOS) is widely used in power management circuits due to its high voltage resistance, high current drive capability and extremely low power consumption. In LDMOS devices, on-resistance is an important indicator. In the BCD (Bipolar-CMOS-DMOS, bipolar-complementary metal oxide semiconductor-double diffused metal oxide semiconductor) process, although DMOS and CMOS are integrated in the same chip, due to the high withstand voltage and low on-resistance Requirements, under the premise that the conditions of the background region and the drift region of DMOS a...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/78H01L29/06H01L21/336
Inventor 钱文生石晶慈朋亮刘冬华
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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