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Intermetallic compound bonding method and structure for three-dimensionally packaged chip stacking

An intermetallic compound and chip stacking technology, which is applied in metal processing equipment, electrical components, circuits, etc., can solve the problems of low bonding strength, long bonding time, and low efficiency, and improve mechanical properties and service life. Reliability, improved bonding efficiency, and good process compatibility

Active Publication Date: 2015-06-17
DALIAN UNIV OF TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The chip stacking bonding in the existing three-dimensional packaging technology has the following disadvantages: the bonding temperature of direct bonding and metal diffusion bonding is high, and the large difference in the thermal expansion coefficient of each layer of material is likely to cause wafer warping, and the bonding pressure is easy to Cracks appear on extremely thin chips (tend to be below 50 μm), and the requirements for the flatness of the bonding surface are extremely high, which increases the difficulty of the process, the bonding time is long, and the efficiency is low; the connection strength of adhesive bonding is low, and the polymer is easy to Deterioration occurs during the service process of the product, which reduces service reliability; although solder bump bonding can avoid the above problems, the interfacial intermetallic compound generated during bonding forms a multi-interface heterogeneous connection with solder and metal bumps. During service, voids or cracks are generated on the interface due to interdiffusion of atoms, which reduces service reliability. In addition, the solder is a low-melting point alloy, which limits solder bump bonding to service at lower temperatures
Existing patents use the method of fully converting the solder and metal bumps into intermetallic compounds to achieve bonding, but the disadvantages are that the brazing reaction time is long, the production efficiency is low, the orientation of the formed intermetallic compounds is random, and Easy to form voids in intermetallic compounds

Method used

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  • Intermetallic compound bonding method and structure for three-dimensionally packaged chip stacking

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Effect test

Embodiment 1

[0055] The intermetallic compound bonding method for three-dimensional packaging chip stacking of the present invention is realized through the following specific process steps:

[0056] Step 1: Provide a chip first substrate 10, electroplate a 5 μm thick array of Cu first metal bumps 20 on the chip first substrate 10, and electroplate a 5 μm thick Sn The first solder layer 22; provide the second substrate 30 of the chip, on the second substrate 30 of the chip, electroplate an array of Cu second metal bumps 40 with a thickness of 15 μm, and electroplate on the second Cu metal bumps 40 5 μm thick Sn second solder layer 42; Cu first metal bumps 20 and Cu second metal bumps 40 have a mirror-symmetrical array pattern;

[0057] Step 2: align the first Sn solder layer 22 and the second Sn solder layer 42 one by one, and place them in face-to-face contact to form an assembly, such as figure 1 shown;

[0058] Step 3: Heating the assembly formed in Step 2 and performing brazing reflo...

Embodiment 2

[0061] The intermetallic compound bonding method for three-dimensional packaging chip stacking of the present invention is realized through the following specific process steps:

[0062] Step 1: Provide a chip first substrate 10, electroplate a 5 μm thick array of Cu first metal bumps 20 on the chip first substrate 10, and electroplate a 10 μm thick Sn The first solder layer 22; the second substrate 30 of the wafer is provided, and an array of Cu second metal bumps 40 with a thickness of 25 μm is electroplated on the second substrate 30 of the wafer, and the second metal bumps 40 of Cu are electroplated. Electroplating a 10 μm thick Sn second solder layer 42; Cu first metal bumps 20 and Cu second metal bumps 40 have a mirror-symmetrical array pattern;

[0063] Step 2: align the first Sn solder layer 22 and the second Sn solder layer 42 one by one, and place them in face-to-face contact to form an assembly, such as figure 1 shown;

[0064] Step 3: Heating the assembly formed ...

Embodiment 3

[0067] The intermetallic compound bonding method for three-dimensional packaging chip stacking of the present invention is realized through the following specific process steps:

[0068] Step 1: Provide a wafer first substrate 10, electroplate an array of Cu first metal bumps 20 with a thickness of 5 μm on the first wafer substrate 10, and electroplate an array of Cu first metal bumps 20 with a thickness of 30 μm A first solder layer 22 of Sn; a second wafer substrate 30 is provided, on which a 30 μm thick array of Cu second metal bumps 40 is electroplated; Cu first metal bumps 20 and Cu second metal bumps 40 have a mirror-symmetrical array pattern;

[0069] Step 2: Align the Sn first solder layer 22 with the Cu second metal bump 40 one by one, and place them in face-to-face contact to form an assembly, such as figure 2 shown;

[0070] Step 3: Heating the assembly formed in Step 2 and performing brazing reflow, so that the temperature of the Cu first metal bump 20 reaches 2...

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Abstract

The invention discloses an intermetallic compound bonding method and structure for three-dimensionally packaged chip stacking. The method comprises the steps that firstly, solder and metal bumps on the two sides of the solder are subjected to thermal treatment to conduct a brazing reaction, and then intermetallic compounds are formed, wherein the temperature gradient is formed between the metal bumps on the two sides of the solder during thermal treatment. When the intermetallic compound bonding structure for three-dimensionally packaged chip stacking is prepared through the method and the metal bumps are single crystals or have preferred orientation, the formed intermetallic compounds have single orientation in the direction of the temperature gradient. In the bonding process, the temperature gradient is introduced to promote metal atoms to conduct thermal migration, forming and growing of interfacial intermetallic compounds are accelerated, and the bonding efficiency is improved remarkably; the intermetallic compounds grow continuously from the cold end at a relatively low temperature to the hot end at a relatively high temperature, and holes can be effectively prevented from existing in the formed intermetallic compounds.

Description

technical field [0001] The invention belongs to the technical field of three-dimensional integration of electronic packaging, and relates to a method and structure for stacking and bonding three-dimensional packaging chips, in particular to a method and structure for bonding intermetallic compounds for stacking three-dimensional packaging chips. Background technique [0002] As electronic packaging devices continue to pursue high frequency, high speed, multi-function, high performance and small size, electronic packaging technology is required to achieve higher integration density and smaller package size, and the packaging structure is gradually developing from two-dimensional to three-dimensional. Multilayer stacked chip bonding is one of the core technologies in three-dimensional electronic packaging. Through Silicon Via (TSV) technology and micro-bump (μ-bump) technology can realize three-dimensional interconnection between chips or between chips and substrates, making u...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/60H01L23/488B23K1/00
Inventor 赵宁黄明亮钟毅赵建飞许利伟马海涛
Owner DALIAN UNIV OF TECH
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