Intermetallic compound bonding method and structure for three-dimensionally packaged chip stacking

Abstract

The invention discloses an intermetallic compound bonding method and structure for three-dimensionally packaged chip stacking. The method comprises the steps that firstly, solder and metal bumps on the two sides of the solder are subjected to thermal treatment to conduct a brazing reaction, and then intermetallic compounds are formed, wherein the temperature gradient is formed between the metal bumps on the two sides of the solder during thermal treatment. When the intermetallic compound bonding structure for three-dimensionally packaged chip stacking is prepared through the method and the metal bumps are single crystals or have preferred orientation, the formed intermetallic compounds have single orientation in the direction of the temperature gradient. In the bonding process, the temperature gradient is introduced to promote metal atoms to conduct thermal migration, forming and growing of interfacial intermetallic compounds are accelerated, and the bonding efficiency is improved remarkably; the intermetallic compounds grow continuously from the cold end at a relatively low temperature to the hot end at a relatively high temperature, and holes can be effectively prevented from existing in the formed intermetallic compounds.

Description

technical field

[0001] The invention belongs to the technical field of three-dimensional integration of electronic packaging, and relates to a method and structure for stacking and bonding three-dimensional packaging chips, in particular to a method and structure for bonding intermetallic compounds for stacking three-dimensional packaging chips. Background technique

[0002] As electronic packaging devices continue to pursue high frequency, high speed, multi-function, high performance and small size, electronic packaging technology is required to achieve higher integration density and smaller package size, and the packaging structure is gradually developing from two-dimensional to three-dimensional. Multilayer stacked chip bonding is one of the core technologies in three-dimensional electronic packaging. Through Silicon Via (TSV) technology and micro-bump (μ-bump) technology can realize three-dimensional interconnection between chips or between chips and substrates, making u...

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