Charge pump circuit in charge pump phase-locked loop

Abstract

The invention discloses a charge pump circuit in a charge pump phase-locked loop. The charge pump circuit comprises a linear region current mirror, a charge-discharge circuit, a copying circuit, a rail-to-rail operational amplification circuit OP1, an RC (Resistance-Capacitance) compensation circuit and two capacitors C1 and C2 used for improving dynamic characteristics. Under the action of common mode negative feedback of a rail-to-rail operational amplification circuit OP2 arranged in the linear region current mirror, the current of the current mirror and the current of the copying circuit can be completely mirrored, the input end of the OP1 is bridged between the charge-discharge circuit and the copying circuit, the current of the charge-discharge circuit and the current of the copying circuit are completely consistent, the charge current and the discharge current of a charge pump are matched, the capacitors C1 and C2 are positioned on the outputs of the OP1 and the OP2 respectively, and the output of an operational amplifier is more stable. The charge pump circuit works under the working voltage of 1V, the charge current and the discharge current in an output voltage range of 0-0.96V can be accurately matched, and the charge current and the discharge current in an output voltage range of 0.04-0.95V have extremely high flatness.

Description

technical field [0001] The present invention relates to a charge pump phase-locked loop (CPPLL), in particular to a charge pump circuit in a charge pump phase-locked loop, which adopts CMOS technology and realizes high-precision current matching in a wide output voltage range by designing a current mirror in a linear region And high current flatness, it can be directly applied to the application of charge pump phase-locked loop circuit in radio frequency and analog integrated circuits. Background technique [0002] The phase-locked loop (PLL) frequency synthesizer circuit uses the principle of feedback to control the output variable, so as to realize the automatic tracking of the frequency of the output signal to the frequency of the input signal. Charge pump phase-locked loop (CPPLL) is the mainstream of current phase-locked loop circuit design. Because of its advantages of wide capture range, short capture time, large linear range, high speed and low power consumption, it ...

AI Technical Summary

Problems solved by technology

In this charge pump (CP) structure, although a cascode structure is added to the charging and discharging circuit and the replica circuit, the purpose is to increase the output impedance and try to keep the charging and discharging current constant in a wide input voltage range, but due to The MOS tubes M23 and M25 of the current leakage work in the saturation region, so that the charge and discharge current cannot reach the value required by the design when the output voltage is small (less than 0.4V). This structure limits the effective matching range of the charge pump, that is, the voltage Controlled Oscillator (VCO) Adjustable Range

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