Electric charge reallocation method for successive approximation analog-digital converter

Abstract

The invention discloses an electric charge reallocation method for a successive approximation analog-digital converter, relating to the field of microelectronics and solid electronics and more particularly to the electric charge reallocation method for the successive approximation analog-digital converter. No extra correction digital-analog converter (DAC) is introduced, and no correction algorithm is introduced. It only needs to disassemble a maximum capacitor into two capacitors, and a first capacitor and a third capacitor are exchanged during two conversions, so as to offset the maximum error of differential non linearity (DNL) / integral non linearity (INL). Compared with a traditional correction method for improving DNL / INL by relying on the correction DAC or the correction algorithm, the electric charge reallocation method makes the structure of the successive approximation analog-digital converter simpler, allows the successive approximation analog-digital converter to occupy a smaller chip area, and makes realization of the successive approximation analog-digital converter on a chip easier.

Description

technical field [0001] It relates to the fields of microelectronics and solid-state electronics, in particular to a charge redistribution method for successive approximation analog-to-digital converters. Background technique [0002] In order to measure the performance and quantization effect of ADC, some performance indicators need to be introduced. The performance indicators of the ADC generally include: Signal-to-Noise Ratio (SNR for short), Spurious Free Dynamic Range (SFDR for short), Signal-to-Noise-and-Distortion Ratio (Signal-to-Noise-and-DistortionRatio, Abbreviated as SNDR), effective accuracy (EffectiveNumberofBits, abbreviated as ENOB), integral nonlinearity (IntegralNonlinearity, abbreviated as INL), differential nonlinearity (DifferentialNonlinearity, abbreviated as DNL), etc., these parameters will affect the design method and structure selection of ADC . Quality factor (FigureofMerit, abbreviated as FOM) is an index to measure the design level of ADC. SARA...

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Problems solved by technology

However, the foreground calibration needs to interrupt the normal operation of the ADC, and cannot track the change of capacitance error with temperature and environment.

Literature [Zhou, YuanandXu, BenweiandChiu, Yun, "A12bit160MS / sTwo-StepSARADCWithBackgroundBit-WeightCalibrationUsingaTime-DomainProximityDetector", IEEEJournalofSolid-StateCircuits, pp.920-931, 2015.] introduces a complex background correction algorithm The mismatch error of the binary capacitor array is corrected, which can track the capacitance error changes caused by power supply voltage and temperature changes in real time. After correction, SNDR is increased from 47.2dB to 50dB, and SFDR is increased from 66.5dB to 85.9dB. Although the linearity is improved after correction Nearly 20dB, but the complex digital post-processing restricts the applicability of the background correction algorithm, and the non-binary capacitor array with a base number less than 2 increases the complexity of the layout design, which has great limitations in practical applications

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