Fabrication method of nanometer t-gate

Abstract

The invention discloses a method for making a nano T-shaped gate, and relates to the technical field of semiconductor device and integrated circuit manufacturing processes. The method comprises the following steps: cleaning and drying a substrate, applying electron beam photoresist to the substrate for the first time, and drying the electron beam photoresist; applying electron beam photoresist for the second time, and directly writing and developing electron beams, and making the upper half of the T-shaped gate; setting different positions, sizes and dosages, and directly writing electron beams on the first electron beam photoresist; developing the first electron beam photoresist, and making the lower half of the T-shaped gate; depositing a gate metal electrode by means of evaporation or sputtering; and stripping metal, removing the photoresist, and completing making of the T-shaped gate. The method is simple in process and easy to implement. The mechanical strength of the nano T-shaped gate and the yield of devices are improved, and the production cost is reduced.

Description

technical field [0001] The invention relates to the technical field of manufacturing technology of semiconductor devices and integrated circuits, in particular to a method for manufacturing a nanometer T-shaped gate. Background technique [0002] Indium phosphide-based, gallium arsenide-based and gallium nitride-based compound semiconductor materials are widely used in the field of ultra-high-speed microelectronics, among which high electron mobility transistors (HEMT) are developing rapidly. Indium phosphide-based HEMTs with a maximum oscillation frequency greater than 1.2THz have been developed internationally using 30nm gate fabrication technology, which is the fastest-working three-terminal device and an ideal device for the transceiver module of the next-generation communication system. [0003] The operating frequency of the HEMT device is closely related to the gate length and gate resistance. Reducing the gate length and reducing the gate resistance can increase the ...

AI Technical Summary

Problems solved by technology

However, the gate length and gate resistance are a pair of contradictions. As the gate length decreases, the gate resistance will also increase, which will reduce the operating frequency of the device. Therefore, T-shaped gates are generally used internationally to reduce gate resistance.

The traditional nano-T gate process can reduce the gate length, but in order to suppress the self-masking effect, the height of the fabricated gate root is low, thereby increasing the parasitic capacitance of the device; another process is to use a dielectric-assisted method to fabricate the T gate. Increased process complexity and increased device manufacturing costs

These two methods will introduce a large gate parasitic capacitance, which will also have a great impact on the frequency of the device.

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