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Nanowire high-electron-mobility transistor integrating nonpolar GaN and preparation method thereof

A technology with high electron mobility and nanowires, which is applied in semiconductor/solid-state device manufacturing, circuits, electrical components, etc., can solve problems such as uneven arrangement of nanowires, low yield, and disorder, and achieve uncontrollability and disorder, optimize the process method, and simplify the effect of process steps

Inactive Publication Date: 2015-12-16
SOUTH CHINA NORMAL UNIVERSITY
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This preparation technology separates the nanowire epitaxial growth from the device preparation, which increases the complexity of the process
Nanowires are transferred by coating with nanowire suspension, which makes the arrangement of nanowires uneven and disordered, and the yield is low, which cannot achieve the purpose of integrated controllable mass production

Method used

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  • Nanowire high-electron-mobility transistor integrating nonpolar GaN and preparation method thereof
  • Nanowire high-electron-mobility transistor integrating nonpolar GaN and preparation method thereof
  • Nanowire high-electron-mobility transistor integrating nonpolar GaN and preparation method thereof

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preparation example Construction

[0042] reference image 3 , The preparation method of integrated non-polar GaN nanowire high electron mobility transistor includes the following steps:

[0043] A. Provide a patterned semiconductor substrate 1 structure. The semiconductor substrate 1 structure includes a substrate 1 and a plurality of square mesa 3 arranged on the substrate 1 at intervals, and each square mesa 3 is provided with an insulating dielectric layer 2;

[0044] B. Etching on the insulating dielectric layer 2 to form a plurality of grooves 4 penetrating the sides of the square mesa 3;

[0045] C. Epitaxially grow heterojunction nanowires 5 on the sidewalls 41 of each groove 4;

[0046] D. A source 6 and a drain 7 are formed on the insulating dielectric layer 2 located on both sides of the heterojunction nanowire 5, and the source 6 and the drain 7 are respectively connected to each heterojunction nanowire 5;

[0047] E. A gate 8 structure is formed between the source 6 and the drain 7. The gate 8 structure inc...

Embodiment 1

[0056] Example 1, combined reference Figure 1 ~ Figure 3 Step A is performed to provide a structure of a semiconductor substrate 1. The structure of the semiconductor substrate 1 includes a substrate 1 and a plurality of square mesa 3 arranged on the substrate 1 at intervals, and each square mesa 3 is provided with an insulating medium Layer 2. The material of the substrate 1 is monocrystalline silicon; the material of the insulating dielectric layer 2 on the substrate 1 is a silicon dioxide layer or silicon nitride, but it is not limited to these two dielectric layers, and may be well-known to those skilled in the art Other dielectric layers. A square mesa 3 is formed on the surface of the semiconductor substrate 1. The square mesa 3 has a length of 100um and a height of 3um. The semiconductor substrate 1 is patterned, and an array of rectangular grooves 4 are formed on the square mesa 3. The rectangular grooves 4 forming the array include: coating a photoresist layer on t...

Embodiment 2

[0060] Example 2, combined reference Figure 1 ~ Figure 3 , A structure of a semiconductor substrate 1 is provided. The structure of the semiconductor substrate 1 includes a substrate 1 and a plurality of square mesa 3 formed on the substrate 1 arranged at intervals, and each square mesa 3 is provided with an insulating dielectric layer 2. The material of the substrate 1 is monocrystalline silicon, and the material of the insulating dielectric layer 2 on the substrate 1 is silicon dioxide layer or silicon nitride, but it is not limited to these two dielectric layers, and can be those skilled in the art. Other known dielectric layers. The square mesa 3 on the surface of the semiconductor substrate 1 has a length of 150um and a height of 3um. The semiconductor substrate 1 is patterned to form an array of rectangular grooves 4. The rectangular grooves 4 forming the array include: coating a photoresist layer on the surface of the silicon dioxide layer; defining the pattern of the...

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Abstract

The invention discloses a nanowire high-electron-mobility transistor integrating nonpolar GaN and a preparation method thereof. The nanowire high-electron-mobility transistor comprises a substrate and an insulated dielectric layer on the substrate. Multiple square tabletops are arranged on the surface of the substrate at intervals. Multiple grooves are etched in the square tabletops. Heterojunction nanowires are grown in the multiple grooves and the square tabletops. A source electrode and a drain electrode are formed in insulated dielectric layer, are arranged on both ends of each heterojunction nanowire respectively and are connected with the heterojunction nanowires. A gate electrode is formed between the source electrode and the drain electrode. A gate dielectric layer is arranged between the gate electrode and the heterojunction nanowires. Epitaxial growth and device preparation are organically unified such that processing steps are greatly simplified and a technique is optimized. The method solves a problem of uncontrollability and disorderedness due to solution dilution coating of a current nanowire transistor, effectively increases the preparative success rate of nanowire transistors, and can be widely used in the semiconductor field.

Description

Technical field [0001] The invention relates to the technical field of semiconductor devices, in particular to an integrated non-polar GaN nanowire high electron mobility transistor and a preparation method thereof. Background technique [0002] Microelectronic integrated circuits and technology are the key factors and core technologies for the rapid development of modern electronic information technology. With the development of microelectronic integration technology, the integration degree of microelectronic devices based on Si materials is getting higher and higher, and the feature size requirements of the devices are getting smaller and smaller. When the minimum feature size is 10nm, the physical limit of microelectronic devices is reached, and Mohr's law no longer holds. This is because nano-semiconductor devices that reach this size have different working mechanisms, materials, and process technologies from microelectronic devices. [0003] Nanoelectronic devices are called...

Claims

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Application Information

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IPC IPC(8): H01L29/778H01L29/06H01L21/335
CPCH01L29/778H01L29/0669H01L29/66462
Inventor 李述体宋伟东李凯王汝鹏
Owner SOUTH CHINA NORMAL UNIVERSITY
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