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Passivation layer structure of power device and manufacturing method thereof

A technology for power devices and passivation layers, which is used in the manufacture of semiconductor/solid-state devices, semiconductor devices, and electric solid-state devices, etc. It can solve the problems of poor control of the uniformity of oxygen content, large interface defects, and influence on the reliability of power devices. , to reduce interface defects, prevent performance degradation, and reduce fixed charges

Active Publication Date: 2016-01-13
FOUNDER MICROELECTRONICS INT
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The present invention provides a passivation layer structure of a power device and a manufacturing method thereof, which are used to solve the problems in the prior art that the uniformity of oxygen content in the passivation structure of the power device is not well controlled, and there are large interface defects that affect the power device. question of reliability

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  • Passivation layer structure of power device and manufacturing method thereof
  • Passivation layer structure of power device and manufacturing method thereof
  • Passivation layer structure of power device and manufacturing method thereof

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Embodiment 1

[0035] figure 1 A schematic cross-sectional view of a passivation layer structure of a power device provided by an embodiment of the present invention, such as figure 1 The power device shown has a silicon wafer 1 , a gate silicon oxide layer 2 , a gate polysilicon layer 3 , a dielectric layer 4 , and a source metal layer 5 . The invention discloses a passivation layer structure of a power device, comprising: a silicon oxide layer 6 formed on the surface of the power device, and an oxygen-doped semi-insulating polysilicon layer 7 formed on the silicon oxide layer 6 .

[0036] Such as figure 1 In the shown passivation layer structure of the power device, the silicon oxide layer 6 is formed on the surface of the power device.

[0037] Specifically, the silicon oxide layer 6 is formed by thermal oxidation, wherein thermal oxidation includes dry oxygen oxidation and wet oxygen oxidation. During thermal oxidation, it is necessary to fill the oxidation equipment with oxygen. The ...

Embodiment 2

[0049] figure 2 A cross-sectional schematic diagram of a passivation layer structure of a power device provided by an embodiment of the present invention; figure 2 The shown passivation layer structure of a power device includes: a silicon oxide layer 6 formed on the surface of the power device, an oxygen-doped semi-insulating polysilicon layer 7 grown on the silicon oxide layer, and the doped A silicon oxynitride layer 8 is formed on the surface of the oxygen semi-insulating polysilicon layer.

[0050] Before the silicon oxide layer 6 is generated, the following steps need to be carried out:

[0051] Using one or more mixed acid solutions of sulfuric acid, hydrochloric acid, nitric acid, and HF acid to clean the power device;

[0052] Fill the oxidation equipment with inert gas and protective gas, raise the temperature to the annealing temperature, and maintain the annealing temperature to perform the first annealing on the power device.

[0053] Specifically, the purpos...

Embodiment 3

[0066] image 3 A schematic cross-sectional view of a passivation layer structure of a power device provided by an embodiment of the present invention; image 3 The shown passivation layer structure of a power device includes: a silicon oxide layer 6 formed on the surface of the power device, an oxygen-doped semi-insulating polysilicon layer 7 grown on the silicon oxide layer, and an oxygen-doped semi-insulating polysilicon layer 7 grown on the A silicon oxide layer 9 is formed on the surface of the semi-insulating polysilicon layer, and a silicon nitride layer 10 is formed on the silicon oxide layer.

[0067] Before the silicon oxide layer 6 is generated, the following steps are also included:

[0068] Using one or more mixed acid solutions of sulfuric acid, hydrochloric acid, nitric acid, and HF acid to clean the power device;

[0069] Fill the oxidation equipment with inert gas and protective gas, raise the temperature to the annealing temperature, and maintain the anneal...

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Abstract

The invention discloses a passivation layer structure of a power device and a manufacturing method thereof. The manufacturing method of the passivation layer structure specifically comprises the steps of generating a silicon oxide layer on the surface of the power device, and generating an oxygen-doped semi-insulating polycrystalline silicon layer on the surface of the silicon oxide layer. Furthermore, the passivation layer structure also comprises at least one of a silicon oxynitride layer, a silicon oxide layer and a silicon nitride layer on the surface of the oxygen-doped semi-insulating polycrystalline silicon layer. According to the invention, the pure silicon oxide layer is grown on the surface of the power device to act as a transition layer before the oxygen-doped semi-insulating polycrystalline silicon layer is generated, the distribution uniformity of the oxygen content of the semi-insulating polycrystalline silicon layer is improved, and interface defects between the passivation structural layers is furthered reduced, thereby solving a problem that the reliability of the power device is affected because of interface defects existing in the passivation structure of the power device in the prior art.

Description

technical field [0001] The invention belongs to the technical field of semiconductor chip manufacturing technology, and in particular relates to a passivation layer structure of a power device and a manufacturing method thereof. Background technique [0002] In the manufacturing process of semiconductor devices, passivating the device surface is one of the key technologies in the manufacturing process. Power devices generally have to work under high current and high voltage for a long time. If the surface is not passivated, the performance of the device will be seriously deteriorated, mainly manifested in: increased leakage current, lower current amplification factor, and creeping breakdown voltage. Change and so on. The main reason for the degradation of device performance is that the surface of unpassivated devices is extremely susceptible to contamination by impurities in the surrounding environment or reacts with chemical components in the surrounding environment, resul...

Claims

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Application Information

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IPC IPC(8): H01L23/29H01L21/56
Inventor 李理马万里赵圣哲
Owner FOUNDER MICROELECTRONICS INT