A 3D memory chip

Abstract

The invention discloses a 3D memory chip. An MRAM (Magnetic Random Access Memory) and a DRAM (Dynamic Random Access Memory) are subjected to mixed use based on a 3D-SIC (3D-Stacked Integrated Circuit) technology to form the 3D memory chip. The 3D memory chip comprises N stacked MRAM chips and M stacked DRAM chips, wherein N is a positive integer and M is a non negative integer; the MRAM chips and the DRAM chips are stacked in the same direction; the MRAM chips and the DRAM chips all adopt DDRDRAM (Double Data Rate Dynamic Random Access Memory) interface standards; and the same lead pins in all the MRAM chips and all the DRAM chips are electrically connected to the same package pin by through silicon vias. On this basis, the invention furthermore provides a multi-chip gating mechanism capable of effectively controlling the chip select signal line quantity.

Description

technical field [0001] The invention relates to a semiconductor memory, in particular to a 3D memory chip. Background technique [0002] In the current computer architecture, software and user data are stored in a hard disk (HD) or a new solid-state drive (SSD, using NAND Flash as a storage medium). The latter is connected to the computer motherboard through serial interfaces such as SATA and PCIe. Computing tasks are performed between the CPU and the memory (such as DRAM), and the communication between the two is carried out through a standard interface protocol (such as the DDR protocol). The packaged memory chips are generally mounted on the main board by patch, or combined into a memory bar and inserted into the corresponding slot provided on the main board. [0003] With the rapid development of computer application technology, the demand for memory performance and capacity is also increasing. [0004] At present, a new type of memory—Magnetic Random Access Memory (M...

AI Technical Summary

Problems solved by technology

[0006] 1. The installation positions of MRAM and DRAM need to be set on the motherboard at the same time, which will occupy more motherboard area and hinder the development of portability and miniaturization of smart devices

[0007] 2. The current memory interface, such as DDR interface, is very cumbersome to route on the motherboard. More memory chips make the design of the motherboard more difficult.

Although adding Base Die / LogicDie is more conducive to memory management, it also increases manufacturing costs and does not support existing memory interface protocols (such as DDR protocol)

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