Method for improving linearity of pipelined successive-approximation analog-to-digital converter

Abstract

The invention discloses a method for improving a linearity of a pipelined successive-approximation analog-to-digital converter. The method is applied to a high-performance analog-to-digital converter in the field of microelectronics and solid-state electronics. The method is characterized in that an ADC sampling rate does not need to be sacrificed; an additional operational amplifier does not need to be introduced to carry out noise shaping; an auxiliary DAC or a slow and accurate ADC does not need to be introduced; a Dither also does not need to be introduced; only capacitors of a first-stage capacitor array of the pipelined successive-approximation analog-to-digital converter need to be grouped; and different capacitor combinations are adopted for each conversion, so that accumulation of errors of capacitor mismatch at the same codon can be avoided. Therefore, compared with a conventional DAC foreground correction method, LMS correction algorithm or correction method for improving a linearity by slow and accurate auxiliary ADC correction, the method disclosed by the invention has effects of no sacrifice of the sampling rate, simpler structure, smaller occupied area of a chip and higher easiness for implementing on a chip.

Description

technical field [0001] The present invention relates to a novel pipelined successive approximation analog-to-digital converter (Pipelined SAR ADC) and a novel capacitive grouping cycle method for improving linearity. performance analog-to-digital converter. Background technique [0002] In recent years, the vigorous development of cloud computing, big data, Internet of Things, robotics, mobile communications, virtual reality and other fields has made human beings dazzled and overwhelmed. So far, no discipline has been as colorful and ever-changing as the field of information technology. Human beings have entered the era of information technology represented by high-tech comprehensive innovation. The development of information technology is extremely rapid. Kraft's law (network value is equal to the square of network nodes) and New Moore's law (Internet bandwidth will double the capacity every 9 months, but the cost will also be reduced by half) continue to work, as some eco...

AI Technical Summary

Problems solved by technology

The auxiliary ADC correction technology has high precision and is easy to integrate on-chip. However, in addition to the design of the main ADC, this correction method also needs to design another more accurate auxiliary ADC, which increases the complexity of the design and increases the power consumption and power consumption of the chip. area

3. Literature Y.Zhou, B.Xu, and Y.Chiu, "A 12 bit 160MS / s Two-Step SAR ADC With Background Bit-WeightCalibration Using a Time-Domain Proximity Detector," IEEE Journal of Solid-State Circuits, 50 (4): 920–931, 2015 disclosed the background LMS correction algorithm. The same input voltage is converted twice. The LMS algorithm calculates the capacitance mismatch error and corrects it according to the difference between the two conversion results of the ADC. Although this algorithm does not need to be accurate Reference source, but the algorithm complexity is high, and it is not easy to implement on-chip

[0005] The research on capacitance mismatch correction technology should first consider that it is easy to realize on-chip. The correction scheme based on LMS algorithm has high precision and good calibration effect, but if the initial value is not selected properly, the algorithm complexity will increase, or even not converge, and it is not easy to implement on-chip. , while the traditional correction technology using two DACs is the easiest to implement on-chip and has the highest success rate, but the power consumption and area are large

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