Unlock instant, AI-driven research and patent intelligence for your innovation.

High withstand voltage semiconductor discrete device chip secondary etching mesa process

A technology of discrete devices and semiconductors, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve problems affecting the filling effect of glass frit on V-shaped grooves, lower product breakdown voltage, and affect product reliability, etc., to achieve Effects of reducing surface leakage, improving dielectric strength, and increasing contact capability

Active Publication Date: 2021-01-26
锦州辽晶电子科技股份有限公司
View PDF9 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Due to the different corrosion rates between silicon dioxide and silicon, small-angle steps are formed at the interface between silicon dioxide and silicon during the corrosion process, which affects the filling effect of the subsequent glass frit on the V-shaped groove, and the V-shaped groove close to the surface of the silicon wafer cannot be completely covered with glass. The powder is filled and covered, so that when the product is tested for voltage, sparks are likely to be generated on the edge of the V-shaped groove, and the increase in surface leakage leads to a decrease in the breakdown voltage of the product, which affects product reliability.

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • High withstand voltage semiconductor discrete device chip secondary etching mesa process
  • High withstand voltage semiconductor discrete device chip secondary etching mesa process
  • High withstand voltage semiconductor discrete device chip secondary etching mesa process

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0025] The steps of the secondary corrosion mesa process for the high withstand voltage semiconductor discrete device chip are as follows:

[0026] 1. If figure 1 As shown, a V-shaped groove is etched on the surface of the silicon wafer 1 with an oxide layer 2 on the surface with a mixed acid solution, and the thickness of the oxide layer on the surface of the silicon wafer is dsio 2 The mixed acid solution is a mixed solution of nitric acid, hydrofluoric acid, and glacial acetic acid, with a volume ratio of 5:3:2. The container containing the mixed acid solution is placed in the mixed solution of ice and water, and the silicon chip is timed in the mixed acid solution. In 3 minutes, the corrosion depth of the measuring groove reaches 75 μm, and the width reaches 180 μm, forming a corrosion table 3 .

[0027] 2. If figure 2 As shown, after the silicon wafer 1 forming the primary etching mesa 3 is subjected to photolithographic masking, the V-shaped groove is subjected to sec...

Embodiment 2

[0036] The steps of the secondary corrosion mesa process for the high withstand voltage semiconductor discrete device chip are as follows:

[0037] 1. If figure 1 As shown, a V-shaped groove is etched with a mixed acid solution on the surface of the silicon wafer with an oxide layer 2 on the surface, and the thickness of the oxide layer on the surface of the silicon wafer is dsio 2 The mixed acid solution is a mixed solution of nitric acid, hydrofluoric acid, and glacial acetic acid, with a volume ratio of 5:3:2. The container containing the mixed acid solution is placed in the ice-water mixed solution, and the silicon chip is timed in the mixed acid solution. In 4 minutes, the corrosion depth of the measuring groove reaches 85 μm, and the width reaches 200 μm, forming a corrosion table 3 .

[0038] 2. If figure 2 As shown, after the silicon wafer 1 forming the primary etching mesa 3 is subjected to photolithography masking, the V-shaped groove is subjected to secondary etc...

Embodiment 3

[0047] The steps of the secondary corrosion mesa process for the high withstand voltage semiconductor discrete device chip are as follows:

[0048] 1. Take two pieces of 3DD155I products in the process, marked as silicon wafer I and silicon wafer II respectively, and the thickness of the oxide layer on the surface of the two silicon wafers is dsio 2 Both are 0.55 μm.

[0049] 2. The two silicon wafers are subjected to a V-groove etching after the mesa photolithography. Place the container containing the mixed solution of nitric acid, hydrofluoric acid, and glacial acetic acid with a volume ratio of 5:3:2 in the ice-water mixture, put two silicon wafers on the rack and put them into the etching solution for timing corrosion, After timing for 3 minutes and 40 seconds, the silicon wafers were taken out to measure the depth and width of the V-groove. The groove mesa depth of the two silicon wafers was 81 μm, and the groove mesa width was 192 μm.

[0050] 3. The silicon wafer I i...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

PropertyMeasurementUnit
depthaaaaaaaaaa
thicknessaaaaaaaaaa
Login to View More

Abstract

A high-voltage-resistant semiconductor discrete device chip secondary etching mesa process, the steps are as follows: perform primary etching on the surface of a silicon chip with an oxide layer on the surface, the depth of primary etching is 75-85 μm; the silicon chip of the V-shaped groove is corroded once, After the photolithographic mask, the V-groove of the primary etching is subjected to secondary etching. The depth of the secondary etching is 7-10 μm, and the width of the secondary etching table is larger than the width of the primary etching table; . After the second etching of the mesa, the small-angle steps caused by the different etching rates of silicon and silicon dioxide near the surface of the silicon wafer are removed, and the groove is filled with glass frit, fused and passivated to connect the surface of the silicon wafer with the V-shaped groove mesa Form a physical buffer zone, increase the contact area between the glass powder and the corrosion table, increase the contact ability, improve the dielectric strength, and reduce the surface leakage, thus ensuring the excellent high temperature, high voltage performance and high reliability of the high withstand voltage semiconductor discrete device chip sex.

Description

technical field [0001] The invention relates to a secondary corrosion mesa process for high withstand voltage semiconductor discrete device chips. [0002] The invention relates to a processing method of a semiconductor device, in particular to a secondary corrosion mesa process for a high withstand voltage semiconductor discrete device chip. Background technique [0003] The traditional mesa semiconductor discrete device chip mostly adopts one-time etching V-groove process, and the etching depth is generally 80-90 μm. Due to the difference in corrosion rate between silicon dioxide and silicon, a small-angle step is formed at the interface between silicon dioxide and silicon during the corrosion process, which affects the filling effect of the subsequent glass frit on the V-shaped groove, and the V-shaped groove close to the surface of the silicon wafer cannot be completely covered with glass. The powder is filled and covered, so that when the product is tested for voltage,...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/306
CPCH01L21/30604H01L21/30608
Inventor 苏舟徐敏丽高广亮刘帅陈浩
Owner 锦州辽晶电子科技股份有限公司