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Method of forming semiconductor device

A semiconductor and device technology, applied in the field of semiconductor device formation, can solve problems such as semiconductor device performance needs to be improved, achieve the effects of reducing process cost and process complexity, reducing aspect ratio requirements, and avoiding damage

Active Publication Date: 2019-07-02
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] However, the performance of semiconductor devices formed by existing technologies still needs to be improved

Method used

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  • Method of forming semiconductor device
  • Method of forming semiconductor device
  • Method of forming semiconductor device

Examples

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no. 1 example

[0037] Figure 4 to Figure 10 It is a structural schematic diagram of the formation process of the semiconductor device in the first embodiment of the present invention.

[0038] refer to Figure 4 , providing a substrate 200 and a dielectric layer 210 on the substrate 200 .

[0039] The base 200 may be a semiconductor substrate, and the semiconductor substrate may be monocrystalline silicon, polycrystalline silicon or amorphous silicon; the semiconductor substrate may also be semiconductor materials such as silicon, germanium, silicon germanium, gallium arsenide, and the like. The semiconductor substrate may further have a semiconductor structure, and the semiconductor structure is a PMOS transistor, an NMOS transistor, a CMOS transistor, a capacitor, a resistor or an inductor. The base 200 may also be a semiconductor substrate and a metal dielectric layer (not shown) on the semiconductor substrate, and the underlying metal layer is located in the metal dielectric layer.

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no. 2 example

[0081] The difference between the second embodiment and the first embodiment is that the thickness of the polysilicon layer is further made at least 1 / 10 of the height of the contact hole formed in the dielectric layer, so that in the process of forming the contact hole in the dielectric layer, it can prevent The etching gas damages the sidewall of the contact hole.

[0082] The height of the contact hole refers to the dimension perpendicular to the surface of the substrate.

[0083] In the process of forming the contact hole, the etching gas is easy to cause damage to the top sidewall of the contact hole. In this embodiment, the thickness of the polysilicon layer is at least 1 / 10 of the height of the contact hole formed in the dielectric layer, so that the etched Etching gas concentrates the position that is easy to cause damage on the sidewall of the polysilicon layer, and because the density of the polysilicon layer is greater than that of the dielectric layer, the polysili...

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Abstract

The invention provides a formation method of a semiconductor device. The formation method comprises the steps that a substrate and a dielectric layer arranged on the substrate are provided; a polysilicon layer, a barrier layer and a graphical mask layer are formed on the dielectric layer from the bottom to the top in turn; the barrier layer, the polysilicon layer and partial thickness of the dielectric layer are etched with the graphical mask layer acting as the mask, and contact holes are formed in the dielectric layer; a conductive layer fully filling in the contact holes is formed on the surface of the graphical mask layer and the contact holes, and the strength of the barrier layer is at least 10 times of the strength of the conductive layer; and the conductive layer and the mask layer are flattened with the barrier layer act as a stop layer. According to the method, the flattening process is enabled to stop on the barrier layer and damage to the dielectric layer can be avoided so that the difference of dielectric layer height and the difference of conductive layer height of different semiconductor devices can be avoided.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for forming a semiconductor device. Background technique [0002] With the continuous advancement of semiconductor integrated circuit process technology, when semiconductor devices are reduced to a deep submicron range, high-performance, high-density connections between semiconductor devices need to be connected through interconnect structures. It is easy to form parasitic resistance and parasitic capacitance in the interconnection structure, resulting in parasitic effect, which leads to the time delay of metal connection transmission. People are faced with how to overcome the RC caused by the rapid growth of connection length (R refers to resistance, C refers to capacitance) A problem with significantly increased latency. [0003] In order to overcome the parasitic effect in the interconnection, in the integrated process of the back-end process interconnectio...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/768
CPCH01L21/76829H01L21/7684
Inventor 张海洋张城龙
Owner SEMICON MFG INT (SHANGHAI) CORP