Method for improving coupling efficiency of flash memory unit by improving ONO capacitance

Abstract

The invention provides a method for improving the coupling efficiency of a flash memory unit by improving ONO capacitance. The method comprises the following steps: flowing the flash memory unit to the step before the technology of forming a floating gate; depositing a floating gate polycrystalline silicon layer on the structure and carrying out chemical and mechanical lapping treatment; carryingout wet etching on a storage cell area part to expose an apex angle of the floating gate; carrying out dry etching on the storage cell area part, and removing a sharp corner of the apex angle of the floating gate so that a smooth structure is formed; and carrying out subsequent fabrication processing flow of the flash memory unit. The method also comprises the step of etching through an isotropouswet process, so that the thickness of a dielectric layer in an ONO surrounded area is reduced, and the capacitance of an ONO area is increased. According to the method for improving the coupling efficiency of the flash memory unit by improving the ONO capacitance provided by the invention, in order to solve the problem that the erasing efficiency of the flash memory unit is reduced caused by lowcoupling efficiency due to the fat that the size of the flash memory unit is continuously decreased, the surrounding of the ONO and the floating gate is improved preferably, the capacitance of the ONOis increased, and the coupling efficiency is improved.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a method for improving the coupling ratio of a flash memory unit by increasing the capacitance of an ONO. Background technique [0002] Flash memory has been widely used as the best choice for non-volatile memory applications due to its advantages of high density, low price, and electrical programmability and erasability. At present, flash memory cells are mainly implemented at the 65nm technology node. With the demand for large-capacity flash memory, the number of chips on each silicon wafer will be reduced by using the existing technology nodes. At the same time, the growing maturity of new technology nodes also urges flash memory cells to be produced with high-node technologies. It means that the size of the flash memory unit needs to be reduced, and the reduced width of the active area of ​​the flash memory unit and the length of the channel ...

AI Technical Summary

Problems solved by technology

[0010] In order to solve the problem that the coupling rate reduction caused by the continuous reduction of the size of the flash memory unit leads to a decrease in the erasing efficiency of the flash memory unit, the present invention proposes a method for improving the coupling rate of the flash memory unit by increasing the ONO capacitance. By improving the ONO and floating gate Surround more, increase the capacitance of ONO, and increase the coupling rate

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