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Semiconductor structure and forming method therefor

A semiconductor and gate structure technology, which is applied in the field of semiconductor structure and its formation, can solve the problems that the performance of semiconductor devices needs to be improved, achieve the effect of improving operating speed and electrical performance, avoiding loss or even gate structure exposure, and avoiding short circuits

Inactive Publication Date: 2018-01-16
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] However, the performance of semiconductor devices formed by the prior art needs to be improved

Method used

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  • Semiconductor structure and forming method therefor
  • Semiconductor structure and forming method therefor
  • Semiconductor structure and forming method therefor

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Embodiment Construction

[0033] It can be seen from the background art that the electrical performance of semiconductor devices formed in the prior art needs to be improved. The reason for combining a semiconductor structure analysis is:

[0034] The semiconductor structure includes: a base; a gate structure located on the base; sidewalls located on the side walls of the gate structure; stress layers located in the bases on both sides of the gate structure; The source-drain doped region within; the dielectric layer on the substrate between the gate structures; the contact hole plug penetrating through the dielectric layer and in contact with the source-drain doped region.

[0035] Wherein, an equivalent capacitance is formed between the gate structure of the semiconductor structure, the contact hole plug located above the gate structure, and the sidewall located on the sidewall of the gate structure, and the operating speed of the semiconductor device is related to the The capacitance value of the ab...

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Abstract

The invention provides a semiconductor structure and a forming method therefor, and the method comprises the steps: providing a substrate; forming a gate structure on the substrate; forming a side wall on a side wall of the gate structure, wherein the side wall is made of a low-k dielectric material; forming a nitrogen-doped layer on the side wall, wherein the percentage of nitrogen atoms in the nitrogen-doped layer is greater than the percentage of the nitrogen atoms in the side wall; forming source-drain doping regions in the substrate at two sides of the gate structure after the forming ofthe nitrogen-doped layer; forming an interlayer dielectric layer covering the gate structure and the substrate; forming a contact hole plug in the interlayer dielectric layer, wherein the contact holeplug makes contact with the source-drain doping regions. According to the invention, the side wall is provided with the nitrogen-doped layer, and the nitrogen-doped layer protects the side wall during the forming of the contact hole plug, and can reduce the etching rate of the etching technology for forming the contact hole plug to the side wall, thereby avoiding a phenomenon that the side wall is damaged or the gate structure is exposed so as to avoid a short circuit fault happening to the contact hole plug and the gate structure, and improving the electrical performances of a semiconductordevice.

Description

technical field [0001] The invention relates to the field of semiconductors, in particular to a semiconductor structure and a forming method thereof. Background technique [0002] With the continuous development of semiconductor process technology, the development trend of semiconductor process nodes following Moore's Law continues to decrease. In order to adapt to the reduction of process nodes, the channel length of MOSFET field effect transistors has to be continuously shortened. The shortening of the channel length has the advantages of increasing the die density of the chip and increasing the switching speed of the MOSFET field effect tube. [0003] However, as the channel length of the device is shortened, the distance between the source and the drain of the device is also shortened, so that the control ability of the gate to the channel becomes worse, resulting in the phenomenon of subthreshold leakage, namely So-called short-channel effects (SCE: short-channel effe...

Claims

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Application Information

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IPC IPC(8): H01L27/04H01L21/8232
Inventor 谢欣云
Owner SEMICON MFG INT (SHANGHAI) CORP
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