Check patentability & draft patents in minutes with Patsnap Eureka AI!

Electric double layer thin film transistor with vertical channel structure and preparation method thereof

A technology of thin-film transistors and vertical channels, applied in transistors, semiconductor/solid-state device manufacturing, circuits, etc., can solve the problems of high cost of industrialization, limited application potential, high driving voltage, etc., and achieve easy 3D integration and low cost The effect of industrialization and strong driving ability

Pending Publication Date: 2018-01-19
SOUTH CHINA UNIV OF TECH
View PDF5 Cites 10 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, most of the common vertical channel structure TFT adopts side gate structure, which requires multiple photolithography and masking, complex process and high cost of industrialization, which is not conducive to its wide application in low-end electronic systems
In addition, traditional TFT devices usually use an oxide insulating film as the gate dielectric layer, the driving voltage is relatively high, and the power consumption of the device is large, which limits its application potential in the fields of flexible, portable, mobile and other electronic systems

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Electric double layer thin film transistor with vertical channel structure and preparation method thereof
  • Electric double layer thin film transistor with vertical channel structure and preparation method thereof
  • Electric double layer thin film transistor with vertical channel structure and preparation method thereof

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0028] like Figure 1a ~ Figure 1c The electric double layer thin film transistor with a vertical channel structure in this embodiment adopts a bottom-gate structure, and sequentially includes a substrate 1, a gate electrode layer 2, an electrolyte gate dielectric layer 3, a source electrode layer 4, and a semiconductor channel layer from bottom to top. 5. The drain electrode layer 6; the electrolyte gate dielectric layer partially covers the gate layer; the source electrode layer completely covers the electrolyte gate dielectric layer; the semiconductor channel layer partially covers the source electrode layer; the drain electrode completely covers the semiconductor channel layer.

[0029] The substrate in this embodiment may be a glass substrate or a plastic substrate.

[0030] The semiconductor channel layer in this embodiment is a 30-60 nanometer indium-doped gallium zinc oxide (IGZO) semiconductor thin film.

[0031] The gate dielectric layer in this embodiment is a fil...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention discloses an electric double layer thin film transistor with a vertical channel structure and a preparation method thereof. The thin film transistor consists sequentially from bottom totop of a substrate, a gate electrode layer, an electrolyte gate dielectric layer, a source electrode layer, a semiconductor channel layer and a drain electrode. The source electrode layer is disposedabove the electrolyte gate dielectric layer. The semiconductor channel layer is disposed above the source electrode layer. The drain electrode is disposed above the semiconductor channel layer. The source electrode layer is a conductive film with an ultra-thin porous structure. The electrolyte gate dielectric layer is made of an electrolyte material having an electric double layer effect. By adopting the vertical channel structure, the thin film transistor of the invention effectively reduces the channel length, thereby increasing the drain electrode current and reducing the operating voltage.According to the invention, the driving capability of the thin film transistor can be effectively enhanced, reduce the power consumption, and the advantages of simple process, low cost, easy integration and the like are gained, and the application in the field of flexible, portable, mobile and wearable low power electronic systems and TFT integrated sensors is facilitated.

Description

technical field [0001] The invention belongs to the technical field of semiconductors, and in particular relates to an electric double-layer thin film transistor with a vertical channel structure and a preparation method thereof. Background technique [0002] In recent years, the application of thin film transistor (TFT) in random access memory (RAM), flat panel imaging, too integrated sensor, especially in display field as AMLCD and AMOLED has attracted extensive attention and research. Over the years, the active layer semiconductor materials used in TFTs have undergone a transformation from silicon-based to oxides, and even to organics, and the performance of various TFTs has also been continuously improved. [0003] In recent years, oxide TFTs represented by zinc oxide are most likely to become the best substitutes for widely used silicon-based TFTs due to their relatively high mobility, high transparency, low-temperature process and many other advantages. For many appli...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/786H01L29/51H01L21/34
Inventor 刘玉荣
Owner SOUTH CHINA UNIV OF TECH
Features
  • R&D
  • Intellectual Property
  • Life Sciences
  • Materials
  • Tech Scout
Why Patsnap Eureka
  • Unparalleled Data Quality
  • Higher Quality Content
  • 60% Fewer Hallucinations
Social media
Patsnap Eureka Blog
Learn More