A method for forming deep via holes

Abstract

The invention provides a method for forming a deep through hole, which belongs to the field of back-illuminated image sensors. An upper buffer layer, a stop layer and a lower buffer layer are formed by setting a stop layer in the buffer layer, and two main etching and two pass Etching forms deep vias. Beneficial effects of the present invention: the present invention can increase buffer layer thickness uniformity by adding stop layer, reduce etching process time, reduce the impact of each deep via rate difference between wafer center and wafer edge, thereby reducing the center-to-edge loading effect, Optimize the process and increase the output.

Description

technical field [0001] The invention relates to the technical field of back-illuminated image sensors, in particular to a method for forming deep through holes. Background technique [0002] In the manufacture of back-illuminated image sensors (Back Side Illumination, BSI), it is necessary to bond two wafers (Device wafer) and signal operation wafer (Logic wafer) to form a composite structure, and then carry out the composite structure. Etching forms a deep via hole, which is used to conduct the two wafers. [0003] Such as figure 1 As shown, it is a schematic diagram of forming a deep through hole in the prior art. From top to bottom, it is an orthoethyl silicate layer (TEOS), an upper silicon oxide buffer layer (BFOX), a metal oxide layer (Hik), and a silicon oxide layer (Hik). layer (Si), silicon oxide dielectric interlayer (ILDOX), carbon-containing silicon nitride (NDC), carbon-containing silicon oxide (BD), carbon-containing silicon nitride (NDC), carbon-containing s...

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Problems solved by technology

[0007] like figure 2 As shown, the current technology adopts the method of ME+OE+cleaning to form DV. During the main etching and over-etching processes, due to the difference in the etching rate between the center of the wafer (or the center of the wafer) and the edge of the wafer, and the difference in the thickness of TPEOX in different composite structures, The BSIN at the edge of the wafer is etched through first, and the BSIN at the center of the wafer is etched through later, resulting in a center-to-edge loading effect during the formation of deep vias, and the edge of the wafer The BSIN is etched and penetrated first, causing the edge of the wafer to expose the TM first, which leads to bond failure and yield loss, which in turn affects wafer acceptance testing (wafer acceptance testing, WAT) and yield (yield)

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