PMOS device and preparation method thereof and computer
A device and process technology, applied in the field of PMOS devices and their preparation methods and computers, can solve the problems of difficulty in preparing PMOS devices, lower crystal quality of epitaxial layers, large lattice mismatch dislocations, etc., to improve crystal quality and work speed Fast, performance-enhancing effects
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Embodiment 1
[0055] See figure 1 , figure 1 A flow chart of a preparation method for a PMOS device provided by an embodiment of the present invention, the preparation method includes:
[0056] (a) select Si substrate;
[0057] (b) making a crystallized SiGe layer on the Si substrate;
[0058] (c) making an N-type strained Ge layer on the crystallized SiGe layer;
[0059] (d) making a grid in the first designated area on the surface of the N-type strained Ge layer;
[0060] (e) making a source region and a drain region respectively in the second designated area and the third designated area of the N-type strained Ge layer;
[0061] (f) Forming a source region electrode and a drain region electrode on the surfaces of the source region and the drain region shown respectively.
[0062] Wherein, in step (a), a single crystal silicon material with a thickness of 2 μm is selected as the Si substrate.
[0063] Further, on the basis of the foregoing embodiments, before step (b), it also inc...
Embodiment 2
[0094] See Figure 3a-Figure 3q , Figure 3a-Figure 3q It is a schematic diagram of a preparation method of a PMOS device according to an embodiment of the present invention, and the preparation method includes the following steps:
[0095] Step 1. Select a single crystal silicon material with a thickness of 2 μm as the Si substrate 001, such as Figure 3a shown.
[0096] Step 2: Utilize the RCA process to clean the Si substrate; then use a hydrofluoric acid solution with a concentration of 10% to clean the Si substrate to remove the oxide layer on the surface of the Si substrate.
[0097] Step 3: At a temperature of 400-500°C, using a magnetron sputtering process, the intrinsic SiGe target material with a purity of 99.999% is 1.5×10 -3 The SiGe layer 002 is deposited on the Si substrate 001 at a process pressure of mb and a deposition rate of 5nm / min. Preferably, the thickness of the SiGe layer 002 is 300-400nm, wherein the composition ratio of Si is 11%, and the Ge The p...
Embodiment 3
[0114] See Figure 4 , Figure 4 A schematic structural diagram of a PMOS device provided by an embodiment of the present invention. The PMOS adopts the second embodiment such as Figure 3a-Figure 3q prepared as indicated. Specifically, the PMOS 300 includes: Si substrate 301, crystallized SiGe layer 302, N-type strained Ge layer 303, gate 304, source region 305, drain region 306, BPSG dielectric layer 307, source region electrode 308, drain region electrode 309, and a SiN passivation layer 310.
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Abstract
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