A voltage-resistant layer of a semiconductor device with three-dimensional laterally variable doping
A semiconductor and voltage-resistant layer technology, applied in semiconductor devices, electrical components, circuits, etc., can solve problems such as breakdown voltage reduction, and achieve the effect of enhancing voltage withstand capability, suppressing three-dimensional curvature effect, and low cost
Active Publication Date: 2020-09-22
NANJING UNIV OF POSTS & TELECOMM +1
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Problems solved by technology
[0006] The technical problem to be solved by the present invention is to overcome the deficiencies of the prior art, provide a semiconductor device voltage-resistant layer with three-dimensional lateral variable doping, solve the electric field concentration effect caused by the three-dimensional effect, obtain a uniform surface electric field, and avoid breakdown voltage the problem of lowering
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[0033] Embodiments of the present invention will be described below in conjunction with the accompanying drawings.
[0034]The present invention designs a voltage-resistant layer of a semiconductor device with three-dimensional lateral variable doping. The voltage-resistant layer is epitaxially formed on the upper surface of the semiconductor substrate or buried oxide layer in the semiconductor device. Specifically, the voltage-resistant layer is directly formed on the semiconductor substrate The upper surface of the bottom is epitaxially formed, or a buried oxide layer is first formed on the semiconductor substrate, and then epitaxially formed on the buried oxide layer; and the withstand voltage layer has three-dimensional lateral variable doping and is heavily doped with P-type or N-type The dopant concentration distribution is nonlinear in the domain-centered structure. In this embodiment, you can use figure 1 As for the semiconductor device described in FIG. 4, the voltag...
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The invention discloses a semiconductor device withstand voltage layer having three-dimensional transverse varied doping. The withstand voltage layer is epitaxially formed on a semiconductor substrateof a semiconductor device or an upper surface of an oxygen-buried layer, the withstand voltage layer has three-dimensional transverse varied doping, in the curvature structure centered on P+ or N+, the doping concentration is nonlinearly distributed. The withstand voltage layer employs interdigitated layout, racetrack layout or circular layout and is made of silicon or silicon carbide, gallium arsenide, indium phosphide and germanium silicon materials, the withstand voltage layer is prepared according to the standard CMOS process, the process is a process scheme completely compatible with thestandard CMOS process, the process is simple for preparation, cost is low, the three-dimensional curvature effect caused by the layout can be effectively inhibited, and withstand voltage capability of actual devices is greatly enhanced.
Description
technical field [0001] The invention relates to a voltage-resistant layer of a semiconductor device with three-dimensional laterally variable doping, and belongs to the technical field of semiconductor power devices. Background technique [0002] As we all know, the breakdown voltage is a key indicator for the optimal design of lateral power devices. In order to obtain the maximum breakdown voltage, it is generally hoped that the surface electric field of the device is completely uniform. Based on this idea, a variation of lateral doping (Variation of Lateral Doping, VLD) technology is proposed and widely used in the optimal design of various power devices. The traditional lateral variable doping technology is based on two-dimensional theory and has been applied to the optimal design of various two-dimensional power devices. The basic structure of SOI lateral power device is RESURF (Reduced Surface Field) structure, figure 1 A typical conventional SOI RESURF LDMOS structu...
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IPC IPC(8): H01L29/06H01L29/78
CPCH01L29/0615H01L29/7816
Inventor 郭宇锋杨可萌张珺李曼姚佳飞张瑛吉新村蔡志匡
Owner NANJING UNIV OF POSTS & TELECOMM