A kind of preparation method of metal interconnection structure

Abstract

The invention provides a preparation method of a metal interconnection structure. The method comprises that a lower dielectric layer with an interconnection line is provided; an etching terminal detection layer rich in nitrogen, a porous interlayer dielectric layer, a low K buffer layer and a metal hard mask layer are formed on the lower dielectric layer successively; a photoresist layer with an open-mounted pattern is formed on the metal hard mask layer, and the cross sectional width of an opening is greater than that of the interconnection line; the metal hard mask layer and the low K bufferlayer are etched to form an opening structure; femto second laser etching is carried out on the porous interlayer dielectric layer by taking the opening structure as a mask; during detection, when the etching terminal detection layer rich in nitrogen is reached by etching, third etching is carried out, and a nitrogen reduction gas is input in the etching process; after that the interconnection line in the lower portion is exposed, nitrogen is input continuously to over etching the lower dielectric layer further and form an opening structure; and a barrier layer, a crystal seed layer and a metal layer are formed successively in the opening structure, and the metal interconnection structure is formed.

Description

technical field [0001] The invention relates to a method for preparing a semiconductor interconnection structure, in particular to a method for preparing a semiconductor interconnection structure with a porous low-K or ultra-low-K interlayer dielectric layer. Background technique [0002] The rapid development of semiconductor integrated circuit technology constantly puts forward new requirements for the development of interconnection technology. At present, in the back-end process of semiconductor manufacturing, in order to connect the integrated circuits composed of various components, metal materials with relatively high conductivity are usually used, but as the size of semiconductor devices continues to shrink, the interconnection structure becomes narrower and narrower. , resulting in higher and higher interconnect resistances. With the help of copper's excellent electrical conductivity, copper interconnection technology has been widely used in the technology of 90nm a...

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Problems solved by technology

[0004] However, the use of low-K or ultra-low-K insulating dielectric materials poses new requirements for semiconductor manufacturing processes. On the one hand, in order to obtain low-K materials or ultra-low-K materials and reduce the K value of materials, the materials usually used are porous materials. However, the mechanical strength of porous materials is relatively low, which leads to easy damage to the insulating dielectric layer during the process of etching through holes or trenches. On the other hand, the porous insulating dielectric layer is easily infiltrated by external materials, causing pollution , reducing the reliability of the material

Existing academic studies have pointed out that the "open" pore structure exposed to the outside when etching the porous dielectric layer can be formed into a closed structure through an additional "plugging" process, so as to prevent metal impurities from easily forming an interconnection structure. However, the additional process not only increases the cost, but also easily changes the shape of the through hole or trench formed by etching, resulting in a less than ideal effect of the final interconnection structure; and usually Next, there are other interconnection structures under the through holes or trenches formed in the interlayer dielectric layer. During etching, it is easy to cause damage to the underlying interconnection structure. At the same time, filling the through holes or trenches During the deposition or heat treatment step, the stress induced between the metal (usually copper) and the underlying interconnection layer is prone to peeling off, making the gap between the metal filled in the via or trench and the underlying interconnection line Poor contact, these will have a great impact on the stability and reliability of semiconductor devices

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