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An 8-bit AES circuit based on double S-cores

A circuit and s-box technology, which is applied to electrical components, encryption devices with shift registers/memory, digital transmission systems, etc., can solve the problems of reduced throughput and increased encryption operation cycles, and achieve improved throughput and reduced Effects of glitch power consumption and extra power consumption reduction

Pending Publication Date: 2018-12-18
SOUTHEAST UNIV +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The AES circuit with an 8-bit data path reduces the number of S-Boxes to only one or two, that is, reduces the power consumption and area by reducing the combinational logic, but the cycle to realize the encryption operation is significantly increased, and the throughput rate is greatly increased. reduce

Method used

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  • An 8-bit AES circuit based on double S-cores
  • An 8-bit AES circuit based on double S-cores
  • An 8-bit AES circuit based on double S-cores

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Embodiment Construction

[0039] The technical solution of the invention will be described in detail below in conjunction with the accompanying drawings.

[0040] The 8-bitAES circuit based on dual S cores designed by the present invention is as figure 1 As shown, it is mainly divided into four modules: data processing module, key expansion module, control module, and key addition module. The input signal of the circuit is the clock signal clk, the reset signal reset, the start signal start_i, the plaintext data_i, the key key_i, and the output signal is the completion signal ready_o and the ciphertext data_o. The work of the circuit can be divided into the following steps:

[0041] Step 1: At the initial startup of the circuit, the control module performs the encryption operation by monitoring the external encryption enable signal start_i. Firstly, the first round of calculation is performed, and the input original plaintext data_i and key key_i are directly input to the key encryption module for encr...

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Abstract

The invention discloses an 8-bit AES circuit based on double S-cores, belonging to the technical field of secure or secure communication devices. The circuit is designed for IoT applications and compared with traditional 128-bit AES circuit, the 8-bit data path is used to reduce the area and power consumption of the circuit and improve the energy efficiency by making full use of serial processingand partial parallel processing. The circuit comprises a data processing module, a key expansion module, a control module and a key addition module. The design of double S-cores enables the data processing module and the key expansion module to execute in parallel. The data processing module makes full use of the idle time when the S cores are not called by the key expansion module to reduce the number of cycles and improve the throughput. At the same time, the shift operation is realized by register-to-register mode, which reduces the intermediate register and further reduces the circuit area.

Description

technical field [0001] The invention discloses an 8-bit AES circuit based on double S cores, and belongs to the technical field of secret or safety communication devices. Background technique [0002] With the rapid development of Internet of Things (Internet of Things, IoT) technology, the market demand for IoT chips is also increasing. As far as the security requirements of the Internet of Things are concerned, due to the large amount of information interaction, data security is a very important issue in the Internet of Things. [0003] In order to ensure information security, encryption algorithms are widely used in System on a Chip (SoC), and the most representative one is Advanced Encryption Standard (AES). The AES algorithm, also known as the Rijndael algorithm, is a symmetric block cipher algorithm in which data is encrypted and decrypted in blocks of 128 bits. [0004] The traditional 128-bit AES uses a 16-byte 128-bit data path, and 64 wiring tracks are used for l...

Claims

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Application Information

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IPC IPC(8): H04L9/08H04L9/06
CPCH04L9/0631H04L9/0891Y02D10/00
Inventor 单伟伟徐嘉铭
Owner SOUTHEAST UNIV