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Gate extraction and injection field effect transistor and its channel carrier control method

A field effect transistor and gate technology, which is applied in the fields of microelectronics technology and semiconductor technology, and can solve the problems of analog integrated circuit signal-to-noise ratio and unfavorable anti-interference ability.

Active Publication Date: 2021-04-20
UNIV OF ELECTRONICS SCI & TECH OF CHINA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the lower operating voltage is very unfavorable to the improvement of the signal-to-noise ratio and anti-interference ability of analog integrated circuits

Method used

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  • Gate extraction and injection field effect transistor and its channel carrier control method
  • Gate extraction and injection field effect transistor and its channel carrier control method
  • Gate extraction and injection field effect transistor and its channel carrier control method

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0085] Example 1: Example with Schottky contacts.

[0086] Gate Extraction / Injection Graphene Field Effect Transistor (referred to as GEIT), on the insulating layer (marked as Substrate), there are gate (marked as G), source (marked as S), drain (marked as D) and a monoatomic layer graphene channel semiconductor region, a gate dielectric layer is arranged between the gate and the channel semiconductor region, and the resistance value of the gate dielectric layer is 109 ~10 12 Ω, the thickness of the channel semiconductor region is 1 atomic layer. The dielectric constant of the gate dielectric layer is 7.5. The material of the channel monoatomic layer graphene channel semiconductor region is an intrinsic semiconductor, the source and drain are metal electrodes, and between the channel semiconductor region and the metal electrode, when the device is turned off, the The base contact is an ohmic contact when the device is turned on. The gate dielectric layer is made of aluminum...

Embodiment 2

[0094] Embodiment 2: An embodiment with a PN junction.

[0095] A gate extraction and injection field effect transistor is provided with a gate, a source, a drain and a channel semiconductor region on the insulating layer, and a gate dielectric layer is provided between the gate and the channel semiconductor region, and the gate dielectric layer is The resistance value is 10 3 ~10 16 Ω, the thickness of the channel semiconductor region is 1-10 atomic layers. The source and the drain are metal electrodes, and the channel semiconductor region and the metal electrodes are in ohmic contact.

[0096] The channel semiconductor region 5 includes two regions of the first conductivity type and one region of the second conductivity type, one region of the first conductivity type is arranged between the source electrode and the region of the second conductivity type, and the other region of the first conductivity type is arranged between the drain and the second conductivity type regi...

Embodiment 3

[0099] Example 3: Example with high and low junctions.

[0100] A gate extraction and injection field effect transistor is provided with a gate, a source, a drain and a channel semiconductor region on the insulating layer, and a gate dielectric layer is provided between the gate and the channel semiconductor region, and the gate dielectric layer is The resistance value is 10 3 ~10 16 Ω, the thickness of the channel semiconductor region is 1-10 atomic layers. The source and the drain are metal electrodes, and the channel semiconductor region and the metal electrodes are in ohmic contact.

[0101] The material of the first conductivity type region is a lightly doped semiconductor, and the material of the second conductivity type region is a heavily doped semiconductor;

[0102] Alternatively, the material of the first conductivity type region is heavily doped semiconductor, and the material of the second conductivity type region is lightly doped semiconductor.

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Abstract

The gate extraction and injection field effect transistor and its channel carrier control method relate to microelectronics technology and semiconductor technology. The gate extraction and injection field effect transistor of the present invention is provided with a source, a drain, a gate and a channel semiconductor region on the insulating layer, and a gate dielectric layer is arranged between the gate and the channel semiconductor region, and is characterized in that, The gate dielectric layer has a resistance value of 10 3 ~10 16 Ω thin film material; the material of the channel semiconductor region is a two-dimensional semiconductor, or a three-dimensional semiconductor with the characteristics of a two-dimensional semiconductor material. The beneficial effect of the invention is that the power consumption of devices and integrated circuits is significantly reduced by orders of magnitude.

Description

technical field [0001] The present invention relates to microelectronic technology and semiconductor technology. Background technique [0002] The development of CMOS integrated circuits using silicon as the semiconductor material has followed Moore's Law for decades. The process size is constantly being scaled down. At present, the 7nm process has reached mass production [1], and is in the stage of developing 5nm [2] and even 3nm process technology [3]. The substrate thickness of silicon integrated circuits is becoming thinner and thinner, and it is gradually developing towards a two-dimensional semiconductor. [0003] The first graphene transistor (GFET) using the monoatomic layer semiconductor graphene was born in 2004 [4]. Since the graphene band gap is zero, before the publication of the Chinese invention patent corresponding to this patent, there has been no report that the graphene GFET made of large-area single atomic layer graphene was turned off. In the embodime...

Claims

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Application Information

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IPC IPC(8): H01L29/786H01L29/51H01L29/24H01L29/16H01L21/336H01L21/34
CPCH01L29/1606H01L29/24H01L29/51H01L29/517H01L29/66742H01L29/66969H01L29/78684H01L29/78603H01L29/78681H01L21/34H01L29/786H01L29/7606H01L29/66037H01L29/0847H01L29/45
Inventor 廖永波李平曾荣周张庆伟李夏
Owner UNIV OF ELECTRONICS SCI & TECH OF CHINA
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