A kind of lateral mosfet device and preparation method thereof

A device and lateral technology, applied in the field of power semiconductors, can solve the problems of poor reverse recovery characteristics, low operating speed, poor reliability, etc., and achieve the effect of improving the electric field concentration effect, reducing the electric field level, and good shielding effect.

Active Publication Date: 2020-11-27
UNIV OF ELECTRONICS SCI & TECH OF CHINA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] The present invention provides a lateral MOSFET device for the problems of poor long-term application reliability caused by excessively high gate dielectric layer electric field, poor reverse recovery characteristics resulting in high power loss, and low operating speed in existing power semiconductor devices in actual circuit applications.

Method used

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  • A kind of lateral mosfet device and preparation method thereof
  • A kind of lateral mosfet device and preparation method thereof
  • A kind of lateral mosfet device and preparation method thereof

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0098] In a lateral silicon carbide MOSFET provided in this embodiment, the device cell structure is as follows: figure 2 As shown, it includes a substrate electrode 12, a P-type silicon carbide substrate 11 and a silicon carbide N- epitaxial layer 9 stacked vertically from bottom to top, and the top layer on one side of the N-type silicon carbide epitaxial layer 9 is provided with silicon carbide N type drain region 10, the top layer on the other side is provided with a silicon carbide N+ source region 7; the upper surface of the silicon carbide N-type drain region 10 is provided with a drain metal 5; it is characterized in that: the silicon carbide N- epitaxial layer 9 The top layer is also provided with a polysilicon region 13; the polysilicon region 13 is adjacent to the silicon carbide N+ source region 7 and is arranged on the side away from the drain metal 5; the upper surface of the polysilicon region 13 and part of the silicon carbide N+ source region 7 The upper surf...

Embodiment 2

[0101] A lateral silicon carbide MOSFET provided in this embodiment, the cell structure of the device in this embodiment is as follows Figure 4 As shown, it differs from Embodiment 1 in that the bottom layer of the polysilicon region 13 of the present invention is set as independent polysilicon partitions, and several narrow-bandgap semiconductor partitions are isolated by the N- epitaxial layer 9 . Such as Figure 4 Shown in the "Area B" area. The conventional design of embodiment 1 same area is as image 3 shown. In this embodiment, the contact area between the integrated diode device and the silicon carbide N-epitaxy 9 is increased, so as to have better on-state performance of the diode.

Embodiment 3

[0103] A lateral silicon carbide MOSFET provided in this embodiment, the cell structure of the device in this embodiment is as follows Image 6 As shown, it differs from Embodiment 1 in that the lateral silicon carbide MOSFET device also has a three-dimensional gate structure, such as Image 6 Shown in area C. The three-dimensional gate structure increases the channel area of ​​the device during forward conduction, thereby optimizing the forward performance of the MOSFET;

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Abstract

A lateral MOSFET device belongs to the technical field of power semiconductor devices. The present invention replaces the contact region and the lower part of the traditional lateral MOSFET device structure with a polysilicon region or a Schottky contact metal region by digging and filling to form a heterojunction or a Schottky contact with rectification characteristics. The mass junction or Schottky contact is a multi-sub device and the conduction voltage drop is lower than that of the traditional parasitic diode, so the reverse recovery characteristics of the device can be optimized, and excellent third-quadrant on-state performance can be achieved; compared with in vitro anti-parallel The diode method significantly reduces the volume of the electronic power system, reduces the packaging cost, reduces the parasitic effect caused by interconnecting wires and interconnecting wires, and thus improves the reliability of the system. At the same time, an optimized design is made to solve the problem of excessively high electric field of the gate dielectric of the device, so that the long-term application reliability of the device can be improved. In addition, the preparation method of the device of the present invention is simple, controllable and easy to implement, which promotes the popularization of semiconductor power devices in many practical applications.

Description

technical field [0001] The invention belongs to the technical field of power semiconductors, and in particular relates to a Lateral-Metal Oxide Semiconductor Field Effect Transistor, a Lateral-MOSFET device and a preparation method thereof. Background technique [0002] Since entering the 21st century, the world's energy production and consumption are still dominated by fossil energy. Combined with the current development and utilization of energy resources, fossil energy will still be the energy basis for human survival and development in a relatively long period of time. However, fossil energy will eventually be exhausted, and it is easy to cause environmental pollution problems. The resulting environmental and sustainable development problems are difficult problems that human beings must face. Electric energy is one of the main forms of energy available to human beings, and improving its utilization efficiency is an important solution to the world's energy problems. The...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/78H01L21/336H01L29/06
CPCH01L29/0684H01L29/66681H01L29/7816
Inventor 张金平邹华赵阳罗君轶刘竞秀李泽宏张波
Owner UNIV OF ELECTRONICS SCI & TECH OF CHINA
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