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Manufacturing method of a magnetic random access memory cell array and peripheral circuit wiring

A technology of random access memory and cell array, which is applied in semiconductor/solid-state device manufacturing, circuits, electrical components, etc. It can solve the problems of MRAM device pollution, damage, time-related dielectric breakdown, etc., and achieve the effect of device electrical performance and yield improvement

Active Publication Date: 2020-08-21
SHANGHAI CIYU INFORMATION TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, since the size of the MTJ structural unit is smaller than that of the VIA x (x>=1) The size of the top opening is small. When etching the magnetic tunnel junction and its bottom electrode, in order to completely isolate the MTJ units, over-etching must be carried out. In the over-etching, the magnetic tunnel junction is not blocked. and its bottom electrode covered copper VIA x (x>=1) area will be partially etched and also damage its diffusion barrier layer (Ta / TaN), which will form copper VIA x (x>=1) to the diffusion channel of the low-k dielectric outside it, Cu atom will be diffused in the low-k dielectric, and this is bound to affect the electrical performance of MRAM, such as: time-dependent dielectric breakdown (TDDB , TimeDependent Dielectric Breakdown) and electron mobility (EM, Electron Mobility), etc., causing damage
[0006] In addition, during the over-etching process of the magnetic tunnel junction and its bottom electrode, due to ion bombardment (IonBombardment), copper atoms and their forming compounds will be sputtered to the sidewall of the magnetic tunnel junction and the etched low-k material surface, causing contamination and electrical shorts to the entire MRAM device

Method used

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  • Manufacturing method of a magnetic random access memory cell array and peripheral circuit wiring
  • Manufacturing method of a magnetic random access memory cell array and peripheral circuit wiring
  • Manufacturing method of a magnetic random access memory cell array and peripheral circuit wiring

Examples

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Embodiment example 1

[0058] Implementation case 1: two single damascene (SD, Single Damascene) processes, the steps are as follows:

[0059] Step 4.1.1: On the dielectric capping layer 403, deposit a top electrode through hole dielectric 501, and use a planarization process to grind the top electrode through hole (TEV) dielectric 501, as shown in FIG. 4(a); the top electrode through hole (TEV) Dielectric 501 is SiO 2 , SiON or low-k and other materials, the thickness of which is 120nm ~ 400nm;

[0060]Step 4.1.2: Graphically define and use an etching process to form a top electrode via (TEV) 502. In the logic area, connect it to the bottom electrode via filling 205. In the storage area, connect it to the top hard mask 402. Usually, a cleaning process is used to remove the polymer after etching, as shown in Figure 4(b);

[0061] Step 4.1.3: fill the metal to form the top electrode through-hole filling 504, and use chemical mechanical polishing (CMP) to grind it flat, as shown in FIG. 4(c); wherei...

Embodiment example 2

[0063] Implementation case 2: one-time double damascene (DD, Dual Damascene) process, such as Figure 5 shown; the steps are as follows:

[0064] Step 4.2.1: On the dielectric capping layer 403, deposit the top electrode through hole dielectric 501, and use the planarization process to grind the top electrode through hole (TEV) dielectric 501 flat, and deposit the metal connection (M x+1 ) dielectric 602; top electrode via (TEV) dielectric 501 is SiO 2 , SiON or low-k and other materials, the thickness of which is 120nm ~ 400nm; metal wiring (M x+1 ) The thickness of dielectric 602 is 50nm~300nm, and its material is SiO 2 , SiON or low-k, etc., usually before deposition, an etch barrier layer 601 with a thickness of tens of nanometers is deposited, and its material is SiN, SiC or SiCN, etc.;

[0065] Step 4.2.2: Graphically define and use an etching process to form the top electrode through hole (TEV) 502 and the metal wiring groove connecting the logic area and the storage...

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Abstract

The invention provides a manufacturing method of a magnetic random memory unit array and peripheral circuit wiring, and provides a manufacturing process and an alignment method for a magnetic random memory device and its surrounding logic circuits between two layers of metal. In the storage area, the bottom electrode through hole, the bottom electrode contact, the magnetic tunnel junction structure unit and the top electrode through hole are sequentially made on the metal connection, and aligned in sequence; in the logic circuit area, the top electrode through hole and the bottom electrode are used The contact is directly connected, and the top electrode through hole, the bottom electrode contact, and the bottom electrode through hole are aligned in sequence; finally, a layer of metal wiring is made on the top electrode through hole to realize the connection between the MRAM logic area and the storage area. Connection. Due to the addition of a layer of bottom electrode contact under the magnetic tunnel junction unit array, the direct connection between the rear copper of the CMOS and the bottom of the magnetic tunnel junction array is effectively cut off, which is beneficial to the improvement of the electrical performance and yield of the device.

Description

technical field [0001] The invention relates to a manufacturing method of a magnetic random access memory (MRAM) unit array and peripheral circuit wiring, and belongs to the technical field of magnetic random access memory (MRAM, Magnetic Radom Access Memory) manufacturing. Background technique [0002] In recent years, MRAM using Magnetic Tunnel Junction (MTJ) is considered to be the future solid-state non-volatile memory, which has the characteristics of high-speed reading and writing, large capacity and low energy consumption. Ferromagnetic MTJ is usually a sandwich structure, which includes: a magnetic memory layer, which can change the magnetization direction to record different data; an insulating tunnel barrier layer in the middle; a magnetic reference layer, located on the other side of the tunnel barrier layer, Its magnetization direction does not change. [0003] In order to record information in this magnetoresistive element, it is suggested to use a writing meth...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/82H01L27/22
CPCH01L21/82H10B61/22
Inventor 肖荣福郭一民陈峻张云森
Owner SHANGHAI CIYU INFORMATION TECH CO LTD