A device and method for generating SVPWM based on a PC/104 bus and an FPGA

Abstract

The invention relates to a device and method for generating SVPWM based on a PC / 104 bus and an FPGA. The device includes a PC / 104 bus, a data acquisition module, a CPU module, an A / D conversion module, wherein the input end of the data acquisition module is connected with an external three-phase line voltage, the output end of the data acquisition module is connected with the input end of the A / Dconversion module, the CPU module is in two-way communication with the PC / 104 bus, and the device also comprises a level conversion module and an FPGA development board; the A / D conversion module is an AD7606 development board; the level conversion module is a level conversion chip SN74LVC4245A; and an 8-bit data line of the A / D conversion module is connected with 8-bit data lines of the FPGA andthe PC / 104 bus through a level conversion chip SN74LVC4245A and Data BIte0-Data BIte7 of the PC / 104 bus, and the FPGA and the PC / 104 bus are in parallel communication. Data transmission is carried outthrough connection between a PC / 104 bus and a control core and between the PC / 104 bus and an FPGA. The time sequence processing capability and the parallel computing capability of the system are enhanced, the problems of data exchange and state control between the PC / 104 bus and the control core 80X86 and between the PC / 104 bus and the FPGA are solved, SVPWM is generated, and the method can be used for driving a three-phase fully-controlled rectifier.

Description

technical field [0001] The invention belongs to the technical field of advanced manufacturing and automatic control, in particular to a device and method for generating SVPWM based on PC / 104 bus and FPGA. Background technique [0002] With the development of power electronic technology, the application of power electronic devices is becoming more and more extensive. Various inverter devices controlled by pulse width modulation (PWM) have been widely used in industry, national defense, transportation and other fields. At present, diode-clamped three-level voltage rectifiers have been widely used in medium-voltage high-power transmission systems. The three-phase rectifier bridge uses a total of 12 rectifier device IGBTs, and the SVPWM signal generated by modulation controls the operation of the IGBTs on the rectifier bridge. When the rectifier works and normally implements PWM control, each bridge arm has two switching tubes connected to the bus terminal at any time, so compa...

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Problems solved by technology

[0003] Most of the SVPWM signal generation technologies based on space current vectors use DSP and CPLD as the control core, which has problems such as complex program design, long development cycle, and difficult peripheral circuit design.

For example, in the article "Research and Design of Three-phase Three-Level SVPWM Rectifier" written by Wu Hainan of Northeastern University in 2013, the DSP and CPLD are used as the control core. Although the DSP is highly integrated, the event manager ( SVPWM necessary module) and ADC sampling module, the ADC module has a total of 16 sampling channels, but only one input signal can be converted at the same time, resulting in a relatively low sampling frequency, in addition, it is necessary to build a sampling signal conditioning circuit, etc. , which affects the overall reliability of the system and increases the complexity of hardware circuit design; the generation of SVPWM has higher requirements for system timing logic processing. Compared with FPGA, CPLD has weaker timing logic processing capability and higher power consumption. Poor flexibility; therefore, using DSP and CPLD as the control core makes the programming process very complicated and not easy to debug

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