System packaging board card structure with heat dissipation structure and manufacturing method of system packaging board card structure

Abstract

Disclosed is a system packaging board card structure with a heat dissipation structure and a manufacturing method of the system packaging board card structure. The system packaging board card structure comprises a ceramic substrate, a large-size chip and a plurality of small-size chips, a plastic package structure, a heat dissipation structure, multiple layers of re-wiring layers and a plurality of components, wherein the front surface and the back surface of the ceramic substrate are coated with metal layers respectively, wiring is formed in the metal layers, and metal bonding areas for correspondingly embedding chips are arranged in the metal layers; the large-size chip and the plurality of small-size chips jointly form the embedded chips, wherein the embedded chips are bonded in the corresponding metal bonding areas of the ceramic substrate; the plastic package structure is encapsulated around the embedded chips; the heat dissipation structure is bonded on the back surface of the ceramic substrate; the multiple layers of the re-wiring layers are located on the upper surface of the plastic package structure and are electrically connected with the embedded chips and the wiring inthe ceramic substrate; a plurality of surface bonding pads are arranged on the upper surfaces of the re-wiring layers, and a non-bonding pad region is covered with an insulating material; and the plurality of components are attached to the surface bonding pads of the multiple layers of the re-wiring layers to form system-level package. The system packaging board card structure has the advantages that the problem of false welding is avoided, the heat dissipation performance is high, the high-density integration is achieved, the signal transmission path can be shortened, the transmission loss can be reduced, and the like.

Description

technical field [0001] The disclosure belongs to the technical field of chip packaging, and relates to a system packaging board structure with a heat dissipation structure and a manufacturing method thereof, in particular to a multi-chip embedded system packaging board structure with a heat dissipation structure and a manufacturing method thereof. The system package board structure with heat dissipation structure forms a system package board, which can be directly inserted into the main board for use. Background technique [0002] With the continuous development of semiconductor technology, the system on chip (SOC, System on a chip) technology has been developed unprecedentedly. More and more transistors are integrated on the SOC chip, and the functions are becoming more and more powerful. Due to the increase in the number of transistors, the size of the SOC chip It is getting bigger and bigger, and the conventional SOC chip of 1 cm x 1 cm to 2 cm x 2 cm can no longer meet t...

AI Technical Summary

Problems solved by technology

[0002] With the continuous development of semiconductor technology, the system on chip (SOC, System on a chip) technology has been developed unprecedentedly. More and more transistors are integrated on the SOC chip, and the functions are becoming more and more powerful. Due to the increase in the number of transistors, the size of the SOC chip It is getting bigger and bigger, and the conventional SOC chip of 1 cm x 1 cm to 2 cm x 2 cm can no longer meet the requirements. At present, it has developed to a chip of 3-4 cm square, and will reach and break through 5 cm x 5 cm in the future.

For the packaging of large-size chips, there are great difficulties in packaging technology

[0003] First of all, in order to meet the performance requirements of the chip and reduce the loss of chip signal transmission, the large-size chip package cannot be packaged by wire bonding, and the chip can only be packaged by flip-chip welding.

It is very difficult to process and manufacture large-sized flip-chip soldering tools and chip flip-chip bonding

After the SMT suction head is installed, the bonding surface of the chip must be controlled to be parallel to the substrate; if there is a slight inclination of the chip during the welding process, even a small inclination will cause a gap between one side of the chip and the substrate after the other side is in contact with the substrate. Large distance, this distance will lead to false soldering, and even some solder balls cannot be soldered to the substrate at all

For example, the size of the chip is 30mm×30mm. If there is a 1° inclination between the chip and the bonded substrate, the side of the chip that is first bonded to the substrate will be 0.52mm lower than the other side. If the chip ball size is <500 microns , then there will be a large number of solder balls that cannot be bonded, forming virtual soldering and missing soldering

During the placement process of the substrate, there must be no warping, and warping will also cause virtual soldering and even some solder balls cannot be soldered

Conventional patch + reflow process, during the reflow process, when the substrate is transferred from the low temperature to the high temperature area, due to the vibration and uneven heating of the substrate, the small warping deformation of the large-size substrate will cause the diagonal of the large-size chip The upper end produces millimeter-level warping, and the solder balls are usually only a few hundred microns in diameter. Therefore, a large number of solder balls will be soldered or even a large number of solder balls will not be soldered.

Similarly, if in-situ patch reflow soldering is used, since the heating is through the suction head and the substrate platform, the temperature distribution on the upper and lower surfaces of the substrate is very uneven, causing the substrate to still warp, and the same false soldering cannot be avoided

Therefore, large-scale chip packaging is extremely difficult

[0004] Secondly, the heat dissipation of large-size chips is an important issue. Heat dissipation during the operation of large-size chips is an important issue for large-size chip packaging. Conventional packaging has a heat sink attached to the back of the chip. For large-size packaging, it has higher heat dissipation requirements. Only relying on a single-sided heat sink cannot meet the heat dissipation requirements

[0005] Therefore, there are still the following technical problems to be solved urgently: large-size chips are packaged using the existing flip-chip soldering technology, which will cause virtual soldering and cannot meet the packaging requirements; Heat dissipation requirements; an independent large-size chip package occupies too much space, resulting in an oversized system with a large-size chip package, which is not conducive to signal transmission and data processing

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