Germanium-silicon-based gallium arsenide material and preparation method thereof, and application of germanium-silicon-based gallium arsenide material

Abstract

The invention provides a germanium-silicon-based gallium arsenide material and a preparation method thereof, and application of a germanium-silicon-based gallium arsenide material. The germanium-silicon-based gallium arsenide material comprises a silicon substrate having a surface with a periodic groove structure, a germanium middle layer attached to the surface of the silicon substrate, and a gallium arsenide layer attached to the surface of the germanium middle layer. The stress is eliminated generated by lattice mismatch of silicon and gallium arsenide by utilizing the inhibiting effect ofthe germanium (113) crystal face on the gallium arsenide antiphase domain and the characteristic of lattice matching of germanium and gallium arsenide, thereby achieving the epitaxial growth of high-quality single-crystal and ultrathin gallium arsenide on the silicon (100) substrate on an III-V family molecular beam epitaxial device.

Description

technical field [0001] The invention relates to a germanium-silicon-based gallium arsenide material and its preparation method and application. Background technique [0002] With the failure of Moore's Law, the development of microelectronic chips is facing unprecedented difficulties. Intel's recent report shows that the amount of data in Google's data center has exceeded 5 Zetabyte (2 70 Byte), Facebook (Facebook) data center investment has exceeded 1 billion US dollars. Therefore, it is imminent to greatly increase the bandwidth of data transmission through silicon optoelectronic integrated chips. As the optical transmission rate of data centers is merged from 100G to 400G era, the hybrid integration of III-V active optoelectronic devices and silicon-based optoelectronic devices has become imperative. Moreover, the demand for light sources on silicon substrates for future chip interconnection is extremely urgent. [0003] The current biggest difficulty in silicon-based...

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Problems solved by technology

[0008] (1) Poor thermal conductivity;

[0009] (2) The bonding yield is not high;

[0010] (3) The sizes of III-V wafers and silicon wafers do not match (III-V: 2-6 inches; silicon: 8-12 inches)

[0012] (1) The silicon small-angle beveled substrate needs special preparation, and is not compatible with the CMOS process, and is an unconventional substrate;

[0013] (2) The difference in thermal expansion coefficient and lattice mismatch lead to a large number of thermal cracks and high-density dislocations;

[0014] (3) The growth structure is extremely complex (dislocation filtering layer and other technologies are required to suppress the extension of threading dislocations), and gallium arsenide with a thickness of more than 2 μm is required

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