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Superjunction n-type mosfet and method of making the same

A manufacturing method and N-type technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve the problems of high substrate manufacturing cost, high cost, impurity diffusion, etc., so as to reduce device cost and epitaxy cost. , the effect of reducing the doping concentration

Active Publication Date: 2022-03-22
SHENZHEN SANRISE TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0009] The first disadvantage is that since the superjunction structure needs to be completely formed in the epitaxial layer, a very thick epitaxial layer needs to be deposited first. The thickness of this epitaxial layer changes with the voltage. 40 micron to 50 micron thick epitaxy, 900V to 1000V devices require 60 micron to 80 micron thick epitaxy
Thicker epi layers are more costly
[0010] The second disadvantage is that the epitaxial layer corresponding to the superjunction structure needs to be deposited on a very high-concentration N-type substrate. Generally, the resistivity of this N-type substrate is 0.001 ohm.cm (ohm.cm) to 0.003 ohm.cm, corresponding to doping concentration 7.36E19cm -3 ~2.25E19cm -3
Such a high-concentration substrate has the following problems. First, the manufacturing cost of the substrate is high. Second, when the high-concentration substrate flows on the production line, the high-concentration impurities may diffuse in the high-temperature process, or in the cleaning process silicon The high-concentration impurities on the slope of the wafer may contaminate the cleaning tank. In particular, most of such high-concentration substrates will be ground off in the final thinning process, which causes a lot of waste
[0011] The super junction structure formed by the existing trench filling method cannot avoid the above two disadvantages

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  • Superjunction n-type mosfet and method of making the same
  • Superjunction n-type mosfet and method of making the same
  • Superjunction n-type mosfet and method of making the same

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Embodiment Construction

[0062] Such as figure 1 As shown, it is a schematic structural diagram of a super-junction N-type MOSFET according to an embodiment of the present invention; the super-junction N-type MOSFET according to an embodiment of the present invention includes:

[0063] An N-type doped semiconductor substrate 1 having a first doping concentration. In the embodiment of the present invention, the semiconductor substrate 1 is a silicon substrate; the subsequent first epitaxial layer 201 and the second epitaxial layer 3 are both silicon epitaxial layers.

[0064] A plurality of grooves 102 are formed on the semiconductor substrate 1. For the grooves 102, please refer to the following Figure 3A shown.

[0065] A first oxide layer 105 a self-aligned with the trench 102 is formed in the semiconductor substrate 1 at the bottom of the trench 102 by oxygen ion implantation or oxygen-containing species implantation and thermal process. For the first oxide layer 105a, please refer to the subse...

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Abstract

The invention discloses an N-type super-junction MOSFET, comprising: a plurality of trenches are formed on a semiconductor substrate; N-type pillars pass through a first epitaxial layer formed on the side of the trench and the semiconductor substrate between the trenches The doping of the N-type pillars is formed by laterally superimposing and diffused by the N-type impurities of the first epitaxial layer, and the P-type pillars are composed of the second epitaxial layer filling the trenches. The thickness of the semiconductor substrate at the bottom of the superjunction structure is defined by the first oxide layer formed by oxygen implantation and heat treatment formed at the bottom of the trench by self-alignment; the drain region is formed on the backside of the thinned semiconductor substrate, and the superjunction A P-type blocking layer formed by backside selective implantation is also formed in the bottom semiconductor substrate. The invention also discloses a manufacturing method of the N-type super-junction MOSFET. The invention can reduce the thickness of the epitaxial layer and the doping concentration of the semiconductor substrate, thereby reducing the cost, improving the consistency of device performance and improving the reverse recovery characteristic of the device.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuits, in particular to a super junction N-type MOSFET; the invention also relates to a manufacturing method of the super junction N-type MOSFET. Background technique [0002] The super junction structure is composed of alternately arranged N-type pillars and P-type pillars. If the superjunction structure is used to replace the N-type drift region in the vertical double-diffused MOS transistor (Vertical Double-diffused Metal-Oxide-Semiconductor, VDMOS) device, the conduction path is provided through the N-type column in the conduction state, and when the conduction The P-type column does not provide a conduction path; in the off state, the PN column jointly bears the reverse bias voltage, forming a super-junction metal-oxide-semiconductor field-effect transistor (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET). The super-junction MOSFET can greatly reduce the on-resistance of...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/78H01L29/06H01L21/336
CPCH01L29/7802H01L29/0634H01L29/66712
Inventor 肖胜安
Owner SHENZHEN SANRISE TECH CO LTD