Sub-threshold digital circuit power consumption optimization method and system

Abstract

The invention discloses a sub-threshold digital circuit power consumption optimization method and system. The method comprises the following steps of: firstly, determining a logic unit circuit capableof reducing performance and power consumption; carrying out time sequence analysis on a given integrated circuit to obtain all signal paths with loose time sequences; determining a plurality of maindelay units capable of reducing performance and power consumption in each signal path with loose time sequence; and finally, increasing or shortening the gate length of the device of the main time delay unit according to a preset time sequence constraint condition so as to optimize the power consumption of the sub-threshold circuit by adjusting the gate length. According to the invention, the gatelength of a device of a main time delay unit is increased or shortened in a reasonable interval; the circuit performance is reduced, the delay time of the unit is prolonged, the power consumption ofthe integrated circuit is reduced on the premise that the time sequence requirement is met, in addition, the power consumption can be reduced and the area can be saved by reducing the gate length, andmeanwhile, the optimization speed is increased.

Description

technical field [0001] The invention relates to the technical field of circuit power consumption optimization, in particular to a sub-threshold digital circuit power consumption optimization method and system. Background technique [0002] Subthreshold digital circuits refer to digital logic circuits whose operating voltage is lower than the threshold voltage of transistor devices. Since the circuit operates in the subthreshold region, the dynamic power consumption and static power consumption of the circuit can be greatly reduced. It is precisely because the device works in the sub-threshold region that the current and voltage of the device have an exponential relationship, and changes in the size of the device will lead to significant changes in current and parasitic capacitance, thereby significantly changing the electrical performance of the circuit. In addition, circuit performance fluctuates greatly with PVT (Process-Voltage-Temperature, process-voltage-temperature) de...

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Problems solved by technology

This will exponentially increase the complexity of device size optimization for subthreshold digital circuits, making the device optimization speed process extremely slow

[0003] At present, with the increase in the scale of sub-threshold digital circuits, the combination of statistical analysis and optimization of PVT deviations with traditional stochastic optimization algorithms and heuristic optimization algorithms has been unable to be directly applied to large-scale sub-threshold digital circuits. Optimization, especially the optimization that cannot be directly applied to large-scale sub-threshold digital sequential circuits

In addition, in order to reduce the power consumption of sub-threshold digital circuits, the performance of sub-threshold digital circuits can be reduced under the premise of meeting the timing requirements. The traditional method is to reduce the gate width / gate length ratio of MOS devices in the circuit. However, reducing the gate width It will cause the discretization of the height of the cells in the standard cell library used, further resulting in a waste of area; and increasing the gate length of the cells working in the subthreshold region may improve the performance of the cells due to the reverse short channel effect, and in random optimization In the algorithm, due to the reverse short channel effect, the device size optimization will fall into the local optimum point

These further increase the complexity of sub-threshold circuit design optimization, resulting in too long optimization time

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