Sub-threshold digital circuit power consumption optimization method and system

A digital circuit and sub-threshold technology, applied in multi-objective optimization, electrical digital data processing, CAD circuit design, etc., can solve the problem of increasing the complexity of device size optimization for sub-threshold digital circuits, increasing the complexity of sub-threshold circuits, Problems such as slow device optimization speed, to achieve the effect of saving area, reducing circuit performance, and optimizing power consumption
CN110956009APending Publication Date: 2020-04-03INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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Patent Information

Authority / Receiving Office
CN Β· China
Patent Type
Applications(China)
Current Assignee / Owner
INST OF MICROELECTRONICS CHINESE ACAD OF SCI
Publication Date
2020-04-03

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Abstract

The invention discloses a sub-threshold digital circuit power consumption optimization method and system. The method comprises the following steps of: firstly, determining a logic unit circuit capableof reducing performance and power consumption; carrying out time sequence analysis on a given integrated circuit to obtain all signal paths with loose time sequences; determining a plurality of maindelay units capable of reducing performance and power consumption in each signal path with loose time sequence; and finally, increasing or shortening the gate length of the device of the main time delay unit according to a preset time sequence constraint condition so as to optimize the power consumption of the sub-threshold circuit by adjusting the gate length. According to the invention, the gatelength of a device of a main time delay unit is increased or shortened in a reasonable interval; the circuit performance is reduced, the delay time of the unit is prolonged, the power consumption ofthe integrated circuit is reduced on the premise that the time sequence requirement is met, in addition, the power consumption can be reduced and the area can be saved by reducing the gate length, andmeanwhile, the optimization speed is increased.
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Description

technical field

[0001] The invention relates to the technical field of circuit power consumption optimization, in particular to a sub-threshold digital circuit power consumption optimization method and system. Background technique

[0002] Subthreshold digital circuits refer to digital logic circuits whose operating voltage is lower than the threshold voltage of transistor devices. Since the circuit operates in the subthreshold region, the dynamic power consumption and static power consumption of the circuit can be greatly reduced. It is precisely because the device works in the sub-threshold region that the current and voltage of the device have an exponential relationship, and changes in the size of the device will lead to significant changes in current and parasitic capacitance, thereby significantly changing the electrical performance of the circuit. In addition, circuit performance fluctuates greatly with PVT (Process-Voltage-Temperature, process-voltage-temperature) de...

Claims

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