Manufacturing method of lateral double-diffused transistor

A technology of lateral double diffusion and manufacturing method, which is applied in the field of manufacturing lateral double diffusion transistors, can solve the problems of LDMOS on-resistance increase and cost increase, and achieve the effects of saving process costs, increasing breakdown voltage, and simplifying process steps

Active Publication Date: 2020-04-03
JOULWATT TECH INC LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] The existing manufacturing process reduces the concentration of the drift region or reduces the overlapping size of the drift region and the gate oxide layer. figure 1 The el

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  • Manufacturing method of lateral double-diffused transistor
  • Manufacturing method of lateral double-diffused transistor
  • Manufacturing method of lateral double-diffused transistor

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Embodiment Construction

[0037] Various embodiments of the invention will be described in more detail below with reference to the accompanying drawings. In the various drawings, the same elements are denoted by the same or similar reference numerals. For the sake of clarity, various parts in the drawings have not been drawn to scale. Also, some well-known parts may not be shown. For the sake of simplicity, the semiconductor structure obtained after several steps can be described in one figure.

[0038] When describing the structure of a device, when a layer or a region is referred to as being "on" or "over" another layer or another region, it may refer to being directly above another layer or another region, or between it and Other layers or regions are also included between another layer and another region. And, if the device is turned over, the layer, one region, will be "below" or "beneath" the other layer, another region.

[0039] If it is to describe the situation directly on another layer or...

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Abstract

The present invention discloses a manufacturing method of a lateral double-diffused transistor. The method comprises the steps that a liner oxide layer and a first hard mask are sequentially depositedon the surface of a substrate, and a P-type well region and an N-type well region which are separated from each other are formed on the substrate; an N-type drift region is formed in the substrate through the opening of the first hard mask, the N-type drift region is spaced apart from the P-type well region and adjacent to the N-type well region; a second hard mask is deposited on the surfaces ofthe first hard mask and the liner oxide layer; and a field oxide layer is formed over the N-type drift region via the opening of the second hard mask. According to the manufacturing method, the opening is formed by etching the first hard mask; a drift region is formed via openings, the mask is saved, and the second hard mask is deposited above the first hard mask, so that the thickness of the nitride layer above the drift region is smaller than that of the nitride layer in other regions, the length of the beak is increased, the electric field of the silicon substrate below a beak region is reduced, and the breakdown voltage of the transistor is effectively improved while the process cost is saved.

Description

technical field [0001] The present invention relates to the technical field of semiconductors, in particular to a method for manufacturing a lateral double-diffused transistor. Background technique [0002] As a type of power field effect transistor, laterally diffused MOS (Lateral Double-Diffused MOSFET, LDMOS) transistor has process compatibility, good thermal stability and frequency stability, high gain, low feedback capacitance and thermal resistance, and constant input impedance, etc. Excellent characteristics, so it has been widely used, and people have higher and higher performance requirements for LDMOS. [0003] In the application of LDMOS, it is required to reduce the source-drain on-resistance Rdson of the device as much as possible under the premise of satisfying the high source-drain breakdown voltage BV-dss, but the optimization requirements of source-drain breakdown voltage and on-resistance are indeed contradictory of. Generally speaking, the way to reduce ...

Claims

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Application Information

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IPC IPC(8): H01L29/78H01L29/40H01L21/336
CPCH01L29/7816H01L29/402H01L29/66681
Inventor 韩广涛陆阳
Owner JOULWATT TECH INC LTD
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