Manufacturing method of lateral double-diffused transistor

Abstract

The present invention discloses a manufacturing method of a lateral double-diffused transistor. The method comprises the steps that a liner oxide layer and a first hard mask are sequentially depositedon the surface of a substrate, and a P-type well region and an N-type well region which are separated from each other are formed on the substrate; an N-type drift region is formed in the substrate through the opening of the first hard mask, the N-type drift region is spaced apart from the P-type well region and adjacent to the N-type well region; a second hard mask is deposited on the surfaces ofthe first hard mask and the liner oxide layer; and a field oxide layer is formed over the N-type drift region via the opening of the second hard mask. According to the manufacturing method, the opening is formed by etching the first hard mask; a drift region is formed via openings, the mask is saved, and the second hard mask is deposited above the first hard mask, so that the thickness of the nitride layer above the drift region is smaller than that of the nitride layer in other regions, the length of the beak is increased, the electric field of the silicon substrate below a beak region is reduced, and the breakdown voltage of the transistor is effectively improved while the process cost is saved.

Description

technical field [0001] The present invention relates to the technical field of semiconductors, in particular to a method for manufacturing a lateral double-diffused transistor. Background technique [0002] As a type of power field effect transistor, laterally diffused MOS (Lateral Double-Diffused MOSFET, LDMOS) transistor has process compatibility, good thermal stability and frequency stability, high gain, low feedback capacitance and thermal resistance, and constant input impedance, etc. Excellent characteristics, so it has been widely used, and people have higher and higher performance requirements for LDMOS. [0003] In the application of LDMOS, it is required to reduce the source-drain on-resistance Rdson of the device as much as possible under the premise of satisfying the high source-drain breakdown voltage BV-dss, but the optimization requirements of source-drain breakdown voltage and on-resistance are indeed contradictory of. Generally speaking, the way to reduce ...

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Problems solved by technology

[0005] The existing manufacturing process reduces the concentration of the drift region or reduces the overlapping size of the drift region and the gate oxide layer. figure 1 The electric field at the star mark shown in the figure can increase the breakdown voltage, but this will increase the on-resistance of LDMOS, or increase the cost of process manufacturing

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