Silicon wafer

A technology for silicon wafers and semiconductors, applied in crystal growth, single crystal growth, single crystal growth, etc., can solve the problems of increased bending of silicon wafers, increased film stress, etc., and achieve the effect of reducing wafer bending and improving suppression

Active Publication Date: 2020-05-15
SUMCO CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In particular, in 3D NAND, each memory element is stacked vertically by dozens or more, and the number of stacked films increases geometrically, so the stress of the film increases proportionally, and the warp of the silicon wafer also increases significantly.

Method used

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Experimental program
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Effect test

Embodiment 1）

[0054] Samples #1 to #16 of silicon wafers having different plane orientations and notch orientations were prepared. Each wafer was grown by the CZ method and had a diameter of 300 mm and a thickness of 775 μm. There are three plane orientations of the wafer sample: (100), (110), and (111). The notch orientations of the plane-oriented (100) wafer are and . The notch orientation of the plane-oriented (110) wafer is There are two types of orientations: and , and two types of notch orientations in the plane-oriented (111) wafer: and . The deviation of the plane orientation and the notch orientation of the wafer used was within ±1 degree.

[0055] Next, the oxygen concentration of each wafer was measured. In addition, all oxygen concentrations are values ​​measured by Fourier transform infrared spectrophotometry (FT-IR) standardized by ASTM F121, 1979.

[0056] Next, when a silicon oxide film with a thickness of 2 μm was formed on the main surfaces of these wafer samples #1 ...

Embodiment 2）

[0064] In the same manner as in Example 1, samples #17 to #31 of silicon wafers having different plane orientations and notch orientations were prepared, and the oxygen concentrations of these wafers were measured.

[0065] Next, after forming a silicon oxide film with a thickness of 1 μm on the main surfaces of these wafer samples #17 to #31 by a CVD process, a part of etching was performed using a mask, and then a silicon nitride film with a thickness of 0.7 μm was formed by a CVD process, and then a silicon nitride film was formed using a mask to The mold is partially etched to produce a Figure 5 The shape of the membrane is shown. For example, in the case of the (100) wafer of sample #17, the silicon oxide film is a rectangular pattern elongated in the orientation, and the silicon nitride film is elongated in a direction perpendicular to the long side direction of the silicon oxide film. rectangle pattern. With this composite pattern, anisotropic film stress is generat...

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Abstract

To provide a silicon wafer which is prevented from being warped during a device process so that the subsequent step, wherein large warp of the wafer would cause problems, can be smoothly carried out.A silicon wafer wherein a multilayered film constituting a semiconductor device layer is formed on one main plane in a device process so that the silicon wafer warps into a cup shape due to the isotropic film stress of the multilayered film. The plane orientation of the silicon wafer is (111).

Description

technical field [0001] The present invention relates to a silicon wafer as a substrate material for semiconductor devices, and more particularly to a silicon wafer suitable as a substrate material for high-stack semiconductor devices such as 3-dimensional NAND flash memory (hereinafter referred to as "3D NAND") and its processing method. Background technique [0002] Recently, 3D NAND has received attention. 3D NAND is a NAND memory in which memory cell arrays are stacked vertically. By setting the number of stacks (number of word lines) to 64 layers, each single crystal can achieve a very large storage capacity of 512Gbit (64GB). capacity. In addition, instead of increasing the density in the plane direction like conventional planar NAND memory, the density in the height direction is increased, and it is possible to provide a high-performance flash memory that not only has a larger capacity, but also has an improved writing speed and excellent power saving. [0003] In t...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): C30B29/06H01L21/02H10B41/20H10B41/35
CPCC30B29/06H01L21/67288H01L21/02005C23C16/402H01L21/02027H01L21/02021H01L21/02381H10B41/20H10B41/35H01L21/0217H01L21/02211H01L21/02274H01L21/022H01L21/02164
Inventor 小野敏昭高奉均
Owner SUMCO CORP
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