Silicon carbide mosfet and preparation method thereof

A silicon carbide and silicon carbide substrate technology, which is used in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve the problems of small inversion layer electron mobility, increased field strength, and SiCMOSFET needs to be improved.

Active Publication Date: 2022-08-09
BYD CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Although it has the above advantages, the electric field concentration effect increases the field strength at the bottom corner of the trench, and the field strength of the gate oxide layer at the MOS interface has exceeded the semiconductor electric field strength, which may cause the gate oxide layer to break down before the PN junction, so Its maximum blocking voltage is limited by the breakdown of the gate oxide layer rather than by the breakdown of the semiconductor; in addition, the electron mobility of the inversion layer is small, especially on the side wall of the trench, so the characteristic on-resistance is large
[0003] Therefore, the current SiC MOSFET still needs to be improved

Method used

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  • Silicon carbide mosfet and preparation method thereof
  • Silicon carbide mosfet and preparation method thereof
  • Silicon carbide mosfet and preparation method thereof

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0049] Preparation methods include:

[0050] Step 1: PECVD epitaxial formation of the first epitaxial layer 31 of n-type SIC on the heavily doped n+ type SIC substrate 2; the doping concentration of the first epitaxial layer 31 is 1×10 15 cm -3 , the thickness is 10 microns, and the doping impurity is nitrogen (N). Figure 5 .

[0051] Step 2: The n-type first epitaxial layer 31 is etched to form a step shape, and the etching depth is 0.1 micron. For the schematic diagram, see Image 6 .

[0052] Step 3: A heavily doped p+ epitaxial layer 121 is epitaxially formed on the etched n-type first epitaxial layer 31 and etched to form the p+ heavily doped region 12; Doping concentration is 1×10 16 cm -3 , the doping impurity is aluminum (Al), and the thickness is 1 micron; such as Figure 7 , Figure 8 shown.

[0053] Step 4: Continue to epitaxially form an n-lightly doped second epitaxial layer 32 on the n-type first epitaxial layer 31 and the p+ heavily doped region 12, an...

Embodiment 2

[0062] Preparation methods include:

[0063] Step 1: MOCVD epitaxial formation of an n-type SIC epitaxial layer 3 on a heavily doped n+-type SIC substrate 2; the doping concentration of the epitaxial layer 3 is 5×10 15 cm -3 , the thickness is 15 microns, and the doping impurity is nitrogen (N). Figure 4 .

[0064] Step 2: Epitaxially forming a p-type epitaxial layer 4 on the n-type epitaxial layer 3; the doping concentration of the p-type SIC lightly doped epitaxial layer 4 is 5×10 13 cm -3 , the doping impurity is aluminum (Al), and the thickness is 2.5 microns; such as Figure 4 shown;

[0065] Step 3: forming an n+ source region 6 and a p+ contact region 5 on the epitaxial layer 4 by photolithography and implantation; the doping concentration of the source region 6 is 1×10 15 cm -3 , the doping concentration of contact region 5 is 5×10 15 cm -3 ; And perform high temperature annealing after implantation, and the annealing temperature is between 1650 °C; such as ...

Embodiment 3

[0072] Preparation methods include:

[0073] Step 1: PECVD epitaxial formation of the first epitaxial layer 31 of n-type SIC on the heavily doped n+ type SIC substrate 2; the doping concentration of the first epitaxial layer 31 is 1×10 16 cm -3 , the thickness is 15 microns, and the doping impurity is nitrogen (N). Figure 5 .

[0074] Step 2: The n-type first epitaxial layer 31 is etched to form a step shape, and the etching depth is 0.4 microns. For the schematic diagram, see Image 6 .

[0075] Step 3: A heavily doped p+ epitaxial layer 121 is epitaxially formed on the etched n-type first epitaxial layer 31 and etched to form the p+ heavily doped region 12; Doping concentration is 1×10 17 cm -3 , the doping impurity is aluminum (Al), and the thickness is 2 microns; such as Figure 7 , Figure 8 shown.

[0076] Step 4: Continue to epitaxially form an n-lightly doped second epitaxial layer 32 on the n-type first epitaxial layer 31 and the p+ heavily doped region 12, ...

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Abstract

The invention provides a silicon carbide MOSFET and a preparation method thereof. The silicon carbide MOSFET comprises a silicon carbide substrate, a lightly doped epitaxial layer of a first conductivity type, a lightly doped epitaxial layer of a second conductivity type, a contact region, a source region, a gate trench, lightly doped implant region, gate oxide layer, gate electrode, dielectric layer, metal electrode and drain. The silicon carbide MOSFET is provided with a first conductivity type lightly doped implantation region on the inner wall of the gate trench, which can effectively increase the carrier concentration in the channel surface region, thereby effectively improving the channel mobility and reducing the channel resistance.

Description

technical field [0001] The invention relates to the technical field of semiconductor devices, in particular to a silicon carbide MOSFET and a preparation method thereof. Background technique [0002] Silicon carbide (SiC), a third-generation semiconductor material, has the characteristics of wide band gap, high critical breakdown electric field, high saturation drift rate, etc., and can work well in extreme scenarios such as high temperature, high frequency, and high power, and thus can be used for Various applications and systems bring significant performance improvements. Among SiC power devices, SiC MOSFET has the advantages of high input impedance, high switching speed stability, and low on-resistance, and is the most concerned SiC switching device. refer to figure 1 In the existing trench SiC MOSFET, an n-SiC drift layer 3 is epitaxially formed on a heavily doped n+ SiC substrate 2, and a p-well 4 is formed on the n-drift layer 3 by implantation. The source region n+...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/78H01L29/06H01L21/336
CPCH01L29/7828H01L29/0684H01L29/66068
Inventor 李俊俏李永辉周维
Owner BYD CO LTD
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