Photoelectric integrated semiconductor device and preparation process thereof
A technology for optoelectronic integration and preparation process, which is applied in the semiconductor field to achieve the effects of improving coupling efficiency, improving process compatibility and saving processes
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Embodiment 1
[0062] See figure 1 , Figure 2a~2t, figure 1 A schematic flow chart of a preparation process for an optoelectronic integrated semiconductor device provided by an embodiment of the present invention, Figure 2a ~2t is a process schematic diagram of a preparation process of an optoelectronic integrated semiconductor device provided by an embodiment of the present invention; the method includes the following steps:
[0063] (a) select the substrate;
[0064] (b) forming a first semiconductor structure and a second semiconductor structure on the substrate;
[0065] (c) forming a first isolation layer on the substrate, the first semiconductor structure, and the second semiconductor structure;
[0066] (d) forming an n++Si layer in the first semiconductor structure while forming an n well in the second semiconductor structure;
[0067] (e) sequentially forming PMOS and NMOS in the second semiconductor structure, and performing rapid annealing on the entire device;
[0068] (f...
Embodiment 2
[0169] See Figure 2a ~2t, Figure 2a˜2t is a process schematic diagram of a fabrication process of an optoelectronic integrated semiconductor device provided by an embodiment of the present invention. On the basis of the above-mentioned embodiments, this embodiment focuses on the detailed description of the fabrication process of a monolithic optically integrated semiconductor device. Specifically, the preparation process includes the following steps:
[0170] S01: Please refer to Figure 2a , the substrate 001 is selected, and the material of the substrate 001 is single crystal silicon; the thickness of the first substrate is 30-750 nm.
[0171] S02: Epitaxially grow a layer of silicon on the substrate 001, and do light p-type impurity doping on the epitaxial layer 002 to form a silicon epitaxial layer 002 with a doping concentration of 10 16 cm -3 ;
[0172] S03: Please refer to Figure 2b , using a dry etching process to carve grooves on the epitaxial layer 002 to f...
Embodiment 3
[0201] See Figure 10 , Figure 10 A schematic structural view of an optoelectronic integrated semiconductor device provided for the implementation of the present invention. On the basis of the foregoing embodiments, this embodiment provides an optoelectronic integrated semiconductor device, which is prepared by any one of the foregoing Embodiments 1 and 2.
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Abstract
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