Check patentability & draft patents in minutes with Patsnap Eureka AI!

Photoelectric integrated semiconductor device and preparation process thereof

A technology for optoelectronic integration and preparation process, which is applied in the semiconductor field to achieve the effects of improving coupling efficiency, improving process compatibility and saving processes

Inactive Publication Date: 2020-06-30
XIAN CREATION KEJI CO LTD
View PDF0 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

There are still many technical problems in the existing OEIC to realize the integration of optical devices and electronic components, including: how to reduce the height difference and spacing between optical devices and electronic components, and improve the structural compatibility of optical devices and electronic components; Process compatibility between devices and electronic devices; how to solve a series of problems such as light coupling efficiency

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Photoelectric integrated semiconductor device and preparation process thereof
  • Photoelectric integrated semiconductor device and preparation process thereof
  • Photoelectric integrated semiconductor device and preparation process thereof

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0062] See figure 1 , Figure 2a~2t, figure 1 A schematic flow chart of a preparation process for an optoelectronic integrated semiconductor device provided by an embodiment of the present invention, Figure 2a ~2t is a process schematic diagram of a preparation process of an optoelectronic integrated semiconductor device provided by an embodiment of the present invention; the method includes the following steps:

[0063] (a) select the substrate;

[0064] (b) forming a first semiconductor structure and a second semiconductor structure on the substrate;

[0065] (c) forming a first isolation layer on the substrate, the first semiconductor structure, and the second semiconductor structure;

[0066] (d) forming an n++Si layer in the first semiconductor structure while forming an n well in the second semiconductor structure;

[0067] (e) sequentially forming PMOS and NMOS in the second semiconductor structure, and performing rapid annealing on the entire device;

[0068] (f...

Embodiment 2

[0169] See Figure 2a ~2t, Figure 2a˜2t is a process schematic diagram of a fabrication process of an optoelectronic integrated semiconductor device provided by an embodiment of the present invention. On the basis of the above-mentioned embodiments, this embodiment focuses on the detailed description of the fabrication process of a monolithic optically integrated semiconductor device. Specifically, the preparation process includes the following steps:

[0170] S01: Please refer to Figure 2a , the substrate 001 is selected, and the material of the substrate 001 is single crystal silicon; the thickness of the first substrate is 30-750 nm.

[0171] S02: Epitaxially grow a layer of silicon on the substrate 001, and do light p-type impurity doping on the epitaxial layer 002 to form a silicon epitaxial layer 002 with a doping concentration of 10 16 cm -3 ;

[0172] S03: Please refer to Figure 2b , using a dry etching process to carve grooves on the epitaxial layer 002 to f...

Embodiment 3

[0201] See Figure 10 , Figure 10 A schematic structural view of an optoelectronic integrated semiconductor device provided for the implementation of the present invention. On the basis of the foregoing embodiments, this embodiment provides an optoelectronic integrated semiconductor device, which is prepared by any one of the foregoing Embodiments 1 and 2.

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

PropertyMeasurementUnit
thicknessaaaaaaaaaa
thicknessaaaaaaaaaa
Login to View More

Abstract

The invention relates to a photoelectric integrated semiconductor device and a preparation process thereof. The preparation process comprises the following steps: forming a first semiconductor structure and a second semiconductor structure on a substrate; forming a first isolation layer; forming an n+ + Si layer, and forming an n trap at the same time; forming a PMOS and an NMOS, and performing rapid annealing on the whole device; etching the part above the n+ + Si layer, and forming an n+ + doped Ge layer, a p+ doped Ge layer, a p+ + doped Si layer and a second isolation layer on the n+ + Silayer in sequence; forming a light emitting structure, a waveguide structure and a detector structure; forming a polysilicon gate and a first electrode; forming a pressure stress film on the waveguidestructure and the NMOS; forming a tensile stress film on the detector structure and the NMOS; and respectively forming second electrodes on the substrate, the detector structure and the first isolation layer. The preparation process of the photoelectric integrated semiconductor device has high process compatibility, the prepared semiconductor device has high device compatibility, and the opticalcoupling efficiency is improved.

Description

technical field [0001] The invention belongs to the technical field of semiconductors, and in particular relates to a photoelectric integrated semiconductor device and a preparation process thereof. Background technique [0002] With the development of optical communication, optical information processing, optical computing, optical display and other disciplines, people have a strong interest in optoelectronic integration with small size, light weight, stable and reliable operation, high-speed operation and high parallelism. The progress of advanced manufacturing technology makes it possible to integrate optical, optical / electrical and electronic components on a single structure or a single substrate, and constitute an optoelectronic integrated circuit (OEIC) with a single function or multiple functions. [0003] OEIC refers to a monolithic optoelectronic integrated circuit that integrates optical devices and electronic components on the same substrate using optoelectronic t...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): H01L31/153H01L31/173H01L31/18
CPCH01L31/153H01L31/173H01L31/1812H01L31/1876Y02P70/50
Inventor 薛磊岳庆冬
Owner XIAN CREATION KEJI CO LTD
Features
  • R&D
  • Intellectual Property
  • Life Sciences
  • Materials
  • Tech Scout
Why Patsnap Eureka
  • Unparalleled Data Quality
  • Higher Quality Content
  • 60% Fewer Hallucinations
Social media
Patsnap Eureka Blog
Learn More