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GaN junction field effect transistor device with core-shell structure and preparation method of device

A field-effect transistor and core-shell technology, which is used in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve problems such as complex preparation processes, and achieve the effects of good electric field uniformity, strong control ability, and improved reliability.

Pending Publication Date: 2020-07-14
NJU OPTOELECTRONICS ENG RES INST CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The traditional junction field effect transistor (JFET) needs to use the regrowth or ion implantation process to realize the p-n junction, and the preparation process is relatively complicated.

Method used

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  • GaN junction field effect transistor device with core-shell structure and preparation method of device
  • GaN junction field effect transistor device with core-shell structure and preparation method of device
  • GaN junction field effect transistor device with core-shell structure and preparation method of device

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Experimental program
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Effect test

Embodiment 1

[0040] Such as Figure 1-4 Shown, a kind of preparation method of core-shell structure GaN-JFET device, its step comprises:

[0041] (1) MOCVD method deposits semi-insulating GaN layer 2 and the first heavily doped n-GaN layer 3 on the surface of sapphire substrate 1, as figure 1 Shown; growth method of semi-insulating GaN: trimethylgallium and NH 3 As Ga source and N source respectively, the carrier gas is H 2 or N 2 , the growth temperature is 1000-1100°C, and the growth time is 3-5h. Growth method of heavily doped n-GaN layer: temperature 950-1050°C, silicon doping concentration 1*1019 cm -3 , growth time 25-30min. Growth of patterned Si on heavily doped n-GaN layer by PECVD and photolithography 3 N 4 Mask layer 4, Si grown after patterning by photolithography 3 N 4 Regular holes are formed on the membrane, and n-GaN nanocolumns are grown in the holes by MBE;

[0042] (2) MBE method on the first heavily doped n-GaN layer, Si 3 N 4 The epitaxial core-shell nano-c...

Embodiment 2

[0046] The core-shell structure GaN-JFET device, its structure includes:

[0047] A sapphire substrate layer;

[0048] A semi-insulating GaN layer grown on the substrate layer with a thickness of 2 μm;

[0049] A first heavily doped n-GaN layer grown on the semi-insulating GaN layer with a thickness of 300nm, patterned Si grown on the heavily doped n-GaN layer 3 N 4 Layer, the thickness of which is 100nm, the n-GaN nanocolumn channel layer grown on the first heavily doped n-GaN layer, the diameter is 200nm, the height is 800nm, and the n-GaN silicon doping concentration is 1*10 18 cm -3 , the p-GaN nano ring grown on the outside of the n-GaN nano column channel layer, p-GaN and n-GaN channel layer form a core-shell p-n junction, p-GaN thickness 150nm, height 600nm, p- The doping concentration of GaN is 1*10 18 cm -3 ;

[0050] It also includes a second heavily doped n-GaN layer on the channel of the n-GaN nanocolumn, the thickness of which is 300nm, and Si between the s...

Embodiment 3

[0054] The core-shell structure GaN junction field effect transistor device, its structure includes:

[0055] a SiC substrate layer;

[0056] A semi-insulating GaN layer grown on the substrate layer with a thickness of 5 μm;

[0057] A first heavily doped n-GaN layer grown on the semi-insulating GaN layer with a thickness of 300nm, patterned Si grown on the heavily doped n-GaN layer 3 N 4 Layer, the thickness of which is 100nm, the n-GaN nanocolumn channel layer grown on the first heavily doped n-GaN layer, the diameter is 200nm, the height is 800nm, and the n-GaN silicon doping concentration is 1*10 18 cm -3 , the p-GaN nano ring grown on the outside of the n-GaN nano column channel layer, p-GaN and n-GaN channel layer form a core-shell p-n junction, p-GaN thickness 150nm, height 600nm, p- The doping concentration of GaN is 1*10 18 cm -3 ;

[0058] It also includes a second heavily doped n-GaN layer on the channel of the n-GaN nanocolumn, the thickness of which is 300n...

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Abstract

The invention discloses a GaN junction field effect transistor device with a core-shell structure and a preparation method of the GaN junction field effect transistor device. According to the method,a second heavily doped n-GaN layer is grown on a sapphire substrate by utilizing an MBE / MOCVD technology to serve as a subsequent drain end ohmic contact layer; a core-shell type nano columnar p-n junction continues to extend, an inner layer n-GaN serves as a channel layer; a heavily doped n-GaN layer extends to serve as a source end ohmic contact layer; a source, a drain and a grid are formed byutilizing etching and electrode evaporation processes after a device structure is grown, so that a GaN-JFET device can be obtained; due to the fact that the channel of the core-shell p-n junction structure is annularly wrapped and clamped, the internal electric field distribution of the core-shell p-n junction structure is more uniform, and the gate has higher control capacity on the channel.

Description

technical field [0001] The invention relates to a GaN junction field effect transistor device with a core-shell structure, belonging to the field of semiconductor devices. Background technique [0002] Junction field-effect transistors are the core devices that constitute complementary transistor logic circuits, current sense amplifiers, analog-to-digital converter drivers, photodiode transimpedance amplifiers, and other circuits or devices that are used in power transmission, transportation, consumer electronics, etc. important applications in other fields. GaN-based field effect transistors have important application prospects in the fields of variable resistors and power amplifiers due to their advantages such as high operating frequency, low on-resistance, high power density, and high breakdown voltage. The traditional junction field effect transistor (JFET) needs to use the regrowth or ion implantation process to realize the p-n junction, and the preparation process is...

Claims

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Application Information

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IPC IPC(8): H01L29/808H01L29/06H01L21/337
CPCH01L29/8083H01L29/0665H01L29/0676H01L29/66909H01L29/66924
Inventor 邵鹏飞郭慧陈敦军谢自力
Owner NJU OPTOELECTRONICS ENG RES INST CO LTD
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