Metal interconnection structure and preparation method thereof

Abstract

The invention provides a metal interconnection structure and a preparation method thereof. The method comprises the steps of forming a groove inwards in one surface of a dielectric layer; forming a ternary alloy layer in the groove, wherein the ternary alloy layer comprises a first alloy component, a second alloy component and a third alloy component, the first alloy component is copper, the second alloy component is manganese, the third alloy component is one of silver, titanium, chromium, cobalt, nickel, zirconium, yttrium, ruthenium, rhodium, palladium, cadmium, iridium, platinum, gold, aluminum, magnesium and selenium, the atom percentage content of the second alloy component in the ternary alloy layer is 0-15%, and the atom percentage content of the third alloy component in the ternary alloy layer is 6-15%; and the ternary alloy layer is subjected to heat treatment at the temperature of 50-800 DEG C to obtain a seed crystal layer.

Description

technical field [0001] The invention relates to the field of semiconductors, in particular to a metal interconnection structure and a preparation method thereof. Background technique [0002] As the size of semiconductor devices is gradually miniaturized, the size of circuit patterns of integrated circuits formed on semiconductor devices is also developing toward miniaturization. Existing studies have shown that in order to suppress copper diffusion in integrated circuits, it is usually necessary to deposit a copper-manganese alloy seed layer by a physical vapor deposition (Physical Vapor Deposition; PVD) process before forming circuit patterns. However, due to the small size of the semiconductor device, when the seed layer cannot be uniformly deposited on the inner surface of the trench, an overhang phenomenon occurs on the top of the trench, which is not conducive to the formation of subsequent circuit patterns. Even, when the overhanging phenomenon is more severe, the to...

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Problems solved by technology

However, due to the small size of the semiconductor device, it is easy to cause when the seed layer cannot be uniformly deposited on the inner surface of the trench, so that the phenomenon of overhang (Overhang) appears on the top of the trench, which is not conducive to the formation of subsequent circuit patterns.

Even, when the overhanging phenomenon is more serious, the top of the trench will be completely sealed, resulting in the inability to form a circuit pattern inside the trench

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