LDMOS manufactured by using Schottky diode as field plate and manufacturing method of LDMOS
A technology of Schottky diodes and field plates, which is applied in transistors, semiconductor/solid-state device manufacturing, electrical components, etc., and can solve the problems of LDMOS lack of withstand voltage and efficiency
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Problems solved by technology
Method used
Image
Examples
Embodiment 1
[0045] This embodiment provides a method for fabricating an LDMOS using a Schottky diode as a field plate, image 3 The flow of the manufacturing method is shown, Figure 4 The effect comparison between the manufacturing method and the Schottky diode manufacturing method is shown. like image 3 As shown, the method of making an LDMOS by using a Schottky diode as a field plate includes the following steps:
[0046] Step S101, preparing a semiconductor substrate.
[0047] Step S102 , forming an N-drift region in the semiconductor substrate, and simultaneously forming a cathode of a high-voltage Schottky diode.
[0048] Step S103 , forming a P-type implant well in the semiconductor substrate, and the P-type implant well is in contact with the N-drift region on the left and right to form a channel region.
[0049] At this time, the production effect of LDMOS is as follows Figure 4 As shown in part A-1, the production effect of the Schottky diode is as follows Figure 4 show...
Embodiment 2
[0066] This embodiment provides an LDMOS fabricated by using a Schottky diode as a field plate, which is fabricated by the method in Embodiment 1, such as Figure 5 As shown, the LDMOS includes:
[0067] semiconductor substrate;
[0068] A P-type implant well 1 and an N-drift region 2 located in the semiconductor substrate, and the N-drift region 2 is also the cathode of a high-voltage Schottky diode;
[0069] a source 3 located in the P-type implanted well, the source comprising a P+ active region and a first N+ active region;
[0070] a drain 6 located in the N-drift region 1, the drain 6 including a second N+ active region;
[0071] a gate 4 located above the P-type implanted well 1 and the N-drift region 2;
[0072] A guard ring 9 of the high-voltage Schottky diode located in the N-drift region 2;
[0073] An alloy barrier region 5 located on the side of the gate 4 close to the N-drift region 2 and above the N-drift region 2, and an alloy region 8 located in the middle...
PUM
Login to View More Abstract
Description
Claims
Application Information
Login to View More 


