High-energy-efficiency shield gate trench MOSFET and manufacturing method thereof

Abstract

The invention relates to the technical field of electronic product design, in particular to a high-energy-efficiency shielding gate trench MOSFET and a manufacturing method thereof. The manufacturingmethod of the high-energy-efficiency shielding gate trench MOSFET is technically characterized by comprising the steps: S1, selecting an N-type substrate, depositing an etching masking layer on the surface of the substrate, and then forming a deep trench structure on the etching masking layer through etching; S2, injecting Photophor into the bottom of the trench; S3, forming a gate oxide layer inthe trench, depositing Poly1, and performing photoetching and etching by using a Poly1 mark to form a required region; S4, depositing silicon oxide on the surface of the substrate, and flattening thesurface of the substrate; S5, forming a cell region on the surface of the substrate through etching; S6, making Poly2 be deposited on the surface of the cell region, and etching the Poly2 back to thesurface of the silicon; S7, forming a P+ region in the deep trench; and S8, forming an N+ region on the surface of the substrate. A second linear variable doping concentration epitaxial layer is formed by matching different injection energy and injection dosages for many times, so as to obtain an MOSFET with low on-resistance RDSON, high current density and high UIS capability under high frequency.

Description

technical field [0001] The invention relates to the technical field of electronic product design, in particular to a high-energy-efficiency shielded gate trench MOSFET and a manufacturing method thereof. Background technique [0002] Due to its low driving power, fast switching speed, and high current characteristics, VDMOS devices are widely used in extreme environments such as aviation, aerospace, and nuclear industries. For a long time, the contradiction between the drain-source breakdown voltage and on-state resistance of VDMOS devices has been a major research difficulty. Compared with the planar MOSFET structure, since the trench gate MOSFET (UMOS) effectively eliminates the JFET area, it has a smaller on-resistance and is widely used in medium and low voltage devices. [0003] At present, there are many methods to optimize the device drain-source on-state resistance, such as selecting the most suitable channel width and depth, optimizing the implant concentration of ...

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Problems solved by technology

Although these methods optimize the on-resistance to a certain extent, they cannot completely solve the above technical problems.

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