Lead bonding structure comprising embedded manifold type micro-channel and preparation method of lead bonding structure
A technology of wire bonding and micro-channel, which is applied in semiconductor/solid-state device components, semiconductor devices, electrical components, etc., can solve the problems of electrical failure of IC devices, large temperature rise of cooling working fluid, incompatibility, etc., and achieve reduction High temperature rise, high heat dissipation efficiency, and extended service life
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[0046] In a specific embodiment, the present invention provides a method of preparing a lead bonding structure comprising an embedding manifold micro track comprising the following steps.
[0047] The chip 100 is supplied, and the chip 100 can be a wafer state or a die.
[0048] In the case where the chip 100 is wafer state, before making embedded micro track 102, the wafer thickness of the chip 100 is first thinned, such as a thickness of 300 to 500 μm, preferably 350-450 μm thickness. The thickness requires that the silicon can still maintain intensity reliability even after the embedded micro tracking of the back chamber is used for heat dissipation. Then, an embedded micro-track 102 is fabricated by the substrate 101 of the chip 100 through the wafer engraving process and the wafer etching process. The etching process includes conventional wet etching and dry etching, dry etching, can include ion milling etching, plasma etching, and deep reactive ion etching. In a specific emb...
Embodiment 1
[0061] First, a chip 100 having a wafer state having a device layer and an electrical I / O PAD is provided. Then, according to the conventional wafer photolithography process, the wafer etching process etching out the embedded micro track 102 in the back cavity of the chip, and the medium test is selected, and the KGD is selected. figure 2 The chip structure shown.
[0062] The flow passage 204 and the flow passage 205 are produced by a conventional milling cutter processing process in a portion structure for forming the PCB adapter plate, and the liquid opening 201 and the liquid opening 202 are produced by a conventional drilling process in all layers. The electrical interconnect wire is then fabricated on a circuit layer for forming a PCB adapter plate, and an electrical PAD structure is produced at one end thereof, and the other end is made. Finally, the resulting layer is laminated after lamination. image 3 The conveyor structure of the manifold channel shown.
[0063] Such ...
Embodiment 2
[0068] According to the method described in Example 1, the difference is first, first provides a chip 100 having a wafer state of the device layer and the electrical I / OPAD. Then, Ti / Cu 100 / 300 nm is prepared by a physical gas phase deposition (PVD) process in the back surface of the chip 100, respectively, as the adhesion layer and seed layer, respectively. Thereafter, according to the conventional wafer photolithography process, the wafer etching process etching into the back chamber of the chip etching into the embedded micro-track 102, and then electroplating Cu / Sn 6 / 2 μm on the seed layer after removing the photoresist. There is a chip structure of solder and embedded micro track 102. After the film is subtracted, the kgd is selected. Among them, the process sequence of PVD + etching + electroplating ensures no metal, reducing the effects of flow in the micro-track. Then, the thickness of about 6 μm was prepared by the electroplating process at the bonding interface of ...
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